Memory and logic integration for system-in-a-package

被引：5
|
作者：
Wang, M [1 ]
Suzuki, K [1 ]
Sakai, A [1 ]
Dai, W [1 ]
机构：
[1] Univ Calif Santa Cruz, Dept Comp Engn, Santa Cruz, CA 95064 USA
来源：
2001 4TH INTERNATIONAL CONFERENCE ON ASIC PROCEEDINGS | 2001年
关键词：
System-in-a-Package (SiP); Chip-on-Chip (CoC); Chip-Laminate-Chip (CLC); Area-IO;
D O I：
10.1109/ICASIC.2001.982696
中图分类号：
TP [自动化技术、计算机技术];
学科分类号：
0812 ;
摘要：
System-in-a-Pack-age (SiP), a generalization of System-on-a-Chip (SoC), provides a cost-effective solution for large-scale memory and logic integration and an attractive alternative for embedded memory. The key elements of SiP memory/logic integration technology include 10 redistribution; solder bumping; and flip chip assembly, Two SiP platforms: Chip-on-Chip technology and Chip-Laminate-Chip technology are introduced in this paper. An innovative configurable area-10 memory architecture for System-in-a-Pack-age is presented. A 512K SRAM chip has been designed to verify this approach.
引用
收藏
页码：843 / 847
页数：5
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