Factorization using binary decision diagrams

被引:4
|
作者
Raddum, Havard [1 ]
Varadharajan, Srimathi [1 ]
机构
[1] Simula UiB, Thormohlensgate 55, N-5006 Bergen, Norway
关键词
Binary decision diagrams; Integer factorization; RSA;
D O I
10.1007/s12095-018-0304-7
中图分类号
TP301 [理论、方法];
学科分类号
081202 ;
摘要
We address the factorization problem in this paper: Given an integer N=pq, find two factors p and q of N such that p and q are of same bit-size. When we say integer multiplication of N, we mean expressing N as a product of two factors p and q such that p and q are of same bit-size. We work on this problem in the light of Binary Decision Diagrams (BDD). A Binary Decision Diagram is an acyclic graph which can be used to represent Boolean functions. We represent integer multiplication of N as product of factors p and q using a BDD. Using various operations on the BDD we present an algorithm for factoring N. All calculations are done over GF(2). We show that the number of nodes in the constructed BDD is O(n3) where n is the number of bits in p or q. We do factoring experiments for the case when p and q are primes as in the case of RSA modulus N, and report on the observed complexity. The multiplication of large RSA numbers (that cannot be factored fast in practice) can still be easily represented as a BDD.
引用
收藏
页码:443 / 460
页数:18
相关论文
共 50 条
  • [21] Reversible Circuit Synthesis Using Binary Decision Diagrams
    Podlaski, Krzysztof
    [J]. PROCEEDINGS OF THE 23RD INTERNATIONAL CONFERENCE ON MIXED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS (MIXDES 2016), 2016, : 235 - 238
  • [22] Synthesis of optical circuits using binary decision diagrams
    Deb, Arighna
    Wille, Robert
    Keszoecze, Oliver
    Shirinzadeh, Saeideh
    Drechsler, Rolf
    [J]. INTEGRATION-THE VLSI JOURNAL, 2017, 59 : 42 - 51
  • [23] Using Datalog with binary decision diagrams for program analysis
    [J]. Whaley, J. (jwhaley@cs.stanford.edu), Asian Association for Foundation of Software; Japan Society for Software Science and Technology; International Information Science Foundation, Japan; University of Tsukuba (Springer Verlag):
  • [24] Zero-suppressed Binary Decision Diagrams Automated Test Assmbly using Zero-suppressed Binary Decision Diagrams
    Fuchimoto K.
    Minato S.-I.
    Ueno M.
    [J]. Transactions of the Japanese Society for Artificial Intelligence, 2022, 37 (05)
  • [25] Partial binary decision diagrams
    Townsend, WJ
    Thornton, MA
    [J]. PROCEEDINGS OF THE THIRTY-FOURTH SOUTHEASTERN SYMPOSIUM ON SYSTEM THEORY, 2002, : 422 - 425
  • [26] Equational binary decision diagrams
    Groote, JF
    van de Poll, J
    [J]. LOGIC FOR PROGRAMMING AND AUTOMATED REASONING, PROCEEDINGS, 2000, 1955 : 161 - 178
  • [27] Timed binary decision diagrams
    Li, ZC
    Zhao, YH
    Min, YH
    Brayton, RK
    [J]. INTERNATIONAL CONFERENCE ON COMPUTER DESIGN - VLSI IN COMPUTERS AND PROCESSORS, PROCEEDINGS, 1997, : 352 - 357
  • [28] A CHARACTERIZATION OF BINARY DECISION DIAGRAMS
    CHAKRAVARTY, S
    [J]. IEEE TRANSACTIONS ON COMPUTERS, 1993, 42 (02) : 129 - 137
  • [29] Compressing Binary Decision Diagrams
    Hansen, Esben Rune
    Rao, S. Srinivasa
    Tiedemann, Peter
    [J]. ECAI 2008, PROCEEDINGS, 2008, 178 : 799 - +
  • [30] FUNCTIONAL TEST GENERATION USING BINARY DECISION DIAGRAMS.
    Abadir, M.S.
    Reghbati, H.K.
    [J]. Computers & mathematics with applications, 1987, 13 (5-6): : 413 - 430