High Resolution Latched Comparator Implemented in 22 nm FD-SOI Process

被引：0

作者：

Jaworski, Zbigniew ^{[1
]}

机构：

[1] Warsaw Univ Technol, Inst Microelect & Optoelect, Ul Koszykowa 75, PL-00662 Warsaw, Poland

来源：

PROCEEDINGS OF THE 25TH INTERNATIONAL CONFERENCE MIXED DESIGN OF INTEGRATED CIRCUITS AND SYSTEM (MIXDES 2018) | 2018年

关键词：

Comparator; flash ADC; FD-SOI; back-gate polarization; mismatch compensation;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents the design of comparator dedicated for high linearity flash ADC, implemented in 22 nm FD-SOI process with 0.8 V supply. The block employs latched dynamic comparator preceded by two-stage preamplifier. The main obstacle to obtain high resolution comparator is transistor's mismatch resulting in relatively high offset voltage of the amplifier. Thus, compensation technique based on trimming of transistor's threshold voltage by means of modulating of hack-gate polarization has been employed. The obtained comparator presents resolution of +/- 3 mV.

引用

页码：149 / 153

页数：5

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