Highly Linear 4-bit Flash ADC Implemented in 22 nm FD-SOI Process

被引：0

作者：

Jaworski, Zbigniew ^{[1
]}

机构：

[1] Warsaw Univ Technol, Inst Microelect & Optoelect, Ul Koszykowa 75, PL-00662 Warsaw, Poland

来源：

PROCEEDINGS OF THE 2019 26TH INTERNATIONAL CONFERENCE MIXED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS (MIXDES 2019) | 2019年

基金：

欧盟地平线“2020”;

关键词：

Flash ADC; thermometer-to-binary encoder; bubble error correction; comparator; FD-SOI; back-gate polarization; mismatch compensation; process variability; CALIBRATION;

D O I：

10.23919/mixdes.2019.8787023

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

This paper presents the design of 4-bit flash type analog-to-digital converter implemented in 22 nm FD-SOI technology with 0.8 V supply voltage. This block is part of original sub-ranging ADC whose working principle is based on the assumption that sub-ADC and sub-DAC exhibit high linearity while they nominal resolutions remain relatively low. The linearity of the presented flash ADC has to be as high as in case of 8-bit converter. Thus, the most challenging task was to design comparator with resolution of +/- 1.5mV. This goal was reached owing to ability offered by the FD-SOI process to trim transistor's threshold voltage by means of modulating the back-gate polarization. The resulting sampling rate is 500 Ms/s.

引用

页码：221 / 226

页数：6

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