Innovative stack-die package - S2BGA

被引:5
|
作者
Wu, L [1 ]
Wang, YP [1 ]
Hsiao, CS [1 ]
机构
[1] Siliconware Precis Ind Co Ltd, Taichung, Taiwan
关键词
D O I
10.1109/ECTC.2002.1008102
中图分类号
T [工业技术];
学科分类号
08 ;
摘要
Stack-die package concept has been emerging 2similar to3 years ago. The major product - stack-die package with Flash and SRAM chips integrated together which is driven by cellular phone for the purpose of size and weight reduction. The basic requirement for these two dies in stacked package is the size difference must be large enough to allow wire bonding process at bottom die if we still want to utilize the low cost, mature wire bonding technology in interconnection. However, this requirement will limit the application in trying to integrate two similar or same size dies into one stack-die package. One solution for this application is to utilize flip chip technology in interconnection to solve the die size difference requirement. One of concerns for this package is the higher assembly cost due to Flip Chip interconnection. Therefore, a low cost, high reliability alternative package structure is created, it is named S2BGA as Fig. 1.(Spacer Stacked Ball Grid Array).
引用
收藏
页码:250 / 253
页数:2
相关论文
共 50 条
  • [21] Resin-reinforcement technology for enhancing solder reliability of D2BGA (die dimension BGA)
    Shoji, Kazutaka
    Sato, Ryoji
    Okadome, Tetsurou
    NEC Research and Development, 1999, 40 (01): : 119 - 124
  • [22] Impact of Ports Reference Choice on S-Parameter Modeling of BGA Package Interconnections
    Occhiali, Marco
    Sanna, Aurora
    Grassi, Flavia
    24TH IEEE WORKSHOP ON SIGNAL AND POWER INTEGRITY (SPI 2020), 2020,
  • [23] A low-cost ceramic BGA package for 50 Gb/s multiplexing circuit
    Shan, L
    Trewhella, J
    Baks, C
    John, R
    Dyckman, W
    O'Connor, D
    Pillai, E
    ELECTRICAL PERFORMANCE OF ELECTRONIC PACKAGING, 2003, : 59 - 62
  • [24] Resin-reinforcement technology for enhancing solder reliability of D2BGA (Die Dimension BGA)
    Shoji, K
    Sato, R
    Okadome, T
    NEC RESEARCH & DEVELOPMENT, 1999, 40 (01): : 119 - 124
  • [25] Development of a Cu/Low-k Stack Die Fine Pitch Ball Grid Array (FBGA) Package for System in Package Applications
    Zhang, Xiaowu
    Lau, John H.
    Premachandran, C. S.
    Chong, Ser-Choong
    Wai, Leong Ching
    Lee, Vincent
    Chai, T. C.
    Kripesh, V.
    Sekhar, Vasarla Nagendra
    Pinjala, D.
    Che, F. X.
    IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY, 2011, 1 (03): : 299 - 309
  • [26] Design of new 3-dimensional (3-D) die stack package and process optimization
    Ko, HS
    Kim, JS
    Yoon, HG
    Paik, KW
    JOURNAL OF THE KOREAN PHYSICAL SOCIETY, 1999, 35 : S759 - S764
  • [27] A study on the characteristic of UV cured die-attach films in stack CSP (Chip scale package)
    Chung, CL
    Fu, SL
    Lin, T
    Lu, A
    Ho, M
    Kuo, D
    Chou, S
    ICM 2003: PROCEEDINGS OF THE 15TH INTERNATIONAL CONFERENCE ON MICROELECTRONICS, 2003, : 365 - 368
  • [28] Finite Element Analysis of Thermal Cycling Reliability of an Extra Large Thermally Enhanced Flip Chip BGA Package with Rotated Die
    Ma, Y. Y.
    Luan, J. E.
    Goh, K. Y.
    Whiddon, J. W.
    Che, F. X.
    Hu, G. J.
    Baraton, X.
    EPTC: 2008 10TH ELECTRONICS PACKAGING TECHNOLOGY CONFERENCE, VOLS 1-3, 2008, : 709 - 715
  • [29] Development of a 65nm Cu/low-k Stack Die FBGA Package for SiP Applications
    Zhang, Xiaowu
    Premachandran, C. S.
    Chong, Ser-Choong
    Wai, Leong Ching
    Lee, Vincent
    Chai, T. C.
    Kripesh, V.
    Lau, John H.
    Sekhar, V. K.
    Wang, Sandy
    Pinjala, D.
    Lee, Charles
    Yeow, Siao Lin
    EPTC: 2008 10TH ELECTRONICS PACKAGING TECHNOLOGY CONFERENCE, VOLS 1-3, 2008, : 379 - +
  • [30] Development of super high-density chip scale package, CG2BGA
    NEC RESEARCH & DEVELOPMENT, 1999, 40 (04): : 472 - 472