Integrated core selection and mapping for mesh based Network-on-Chip design with irregular core sizes

被引:4
|
作者
Soumya, J. [1 ]
Kumar, K. Naveen [2 ]
Chattopadhyay, Santanu [3 ]
机构
[1] BITS Pilani, Dept Elect & Elect Engn, Hyderabad, Andhra Pradesh, India
[2] Mentor Graph India Pvt Ltd, Noida, India
[3] IIT Kharagpur, Dept Elect & Elect Commun Engn, Kharagpur, W Bengal, India
关键词
Application task graph; Communication cost; Core selection; Mapping; Particle Swarm Optimization; ENERGY-AWARE; STRATEGIES;
D O I
10.1016/j.sysarc.2015.07.014
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
Network-on-Chip (NoC) has been proposed to replace traditional bus based System-on-Chip (SoC) architecture to address the global communication challenges in nanoscale technologies. A major challenge in NoC based system design is to select Intellectual Property (IP) cores for implementing tasks and associate the selected cores to the routers to optimize cost and performance. These are commonly known as the process of core selection and application mapping respectively. In this paper, integrated core selection and mapping problem has been addressed. Mesh architecture has been considered for experimentation. The integrated core selection and mapping problem takes as input the application task graph, topology graph and a core library. It outputs the selected cores for the tasks and their mapping onto the topology graph, such that, all communication requirements of the application are satisfied. The cores present in a core library may perform more than one task and have non-uniform sizes. For this, a technique based on Particle Swarm Optimization (PSO) has been proposed to select cores from the given core library and map the resultant core graph onto mesh based architectures. An efficient heuristic for mapping has also been proposed, which maps the selected cores onto mesh based architectures, considering non-uniform core sizes. Comparisons have been carried out with step-by-step core selection and mapping approach and also with mapping algorithms that exist in the literature. Significant reductions have been observed in terms of communication cost over all the cases. Area comparisons have also been made. On average, improvement of 13.05% in communication cost and 2.07% in area have been observed. The proposed approach has also been compared in dynamic environment and significant reductions in the average network latency could be observed. On average, improvement of 5.48% in average network latency and 15.68% in network throughput has been observed. Comparison of energy consumption has also been done in both the cases. (C) 2015 Elsevier B.V. All rights reserved.
引用
收藏
页码:410 / 422
页数:13
相关论文
共 50 条
  • [31] Torus Topology based Fault-Tolerant Network-on-Chip Design with Flexible Spare Core Placement
    Bhanu, P. Veda
    Kulkarni, Pranav
    Soumya, J.
    Cenkeramaddi, Linga Reddy
    Idsoe, Henning
    [J]. 2018 14TH CONFERENCE ON PHD RESEARCH IN MICROELECTRONICS AND ELECTRONICS (PRIME 2018), 2018, : 97 - 100
  • [32] Deadline and energy aware dynamic task mapping and scheduling for Network-on-Chip based multi-core platform
    Chatterjee, Navonil
    Paul, Suraj
    Mukherjee, Priyajit
    Chattopadhyay, Santanu
    [J]. JOURNAL OF SYSTEMS ARCHITECTURE, 2017, 74 : 61 - 77
  • [33] Temperature-aware multi-application mapping on network-on-chip based many-core systems
    Cao, Shan
    Salcic, Zoran
    Li, Zhaolin
    Wei, Shaojun
    Ding, Yingtao
    [J]. MICROPROCESSORS AND MICROSYSTEMS, 2016, 46 : 149 - 160
  • [34] DESIGN OF A MULTICAST ROUTER FOR NETWORK-ON-CHIP ARCHITECTURES WITH IRREGULAR TOPOLOGIES
    Tseng, Hsi-Che
    Ye, Zhi-Hong
    Chi, Hsin-Chou
    [J]. PROCEEDINGS OF THE 5TH INTERNATIONAL CONFERENCE ON COMPUTING & INFORMATICS, 2015, : 570 - 575
  • [35] Fault-Tolerant Application Mapping on Mesh-of-Tree based Network-on-Chip
    Bhanu, P. Veda
    Soumya, J.
    [J]. JOURNAL OF SYSTEMS ARCHITECTURE, 2021, 116
  • [36] A Communication Probability-Based Mapping Algorithm for Mesh-Based Network-on-Chip Systems
    Sun, Jin
    Zhang, Yi
    [J]. JOURNAL OF CIRCUITS SYSTEMS AND COMPUTERS, 2018, 27 (14)
  • [37] Cost Aware Task Scheduling And Core Mapping on Network-on-Chip topology using Firefly Algorithm
    Umamaheswari, S.
    Kirthiga, Indu K.
    Abinaya, B. S.
    Ashwin, D.
    [J]. 2013 INTERNATIONAL CONFERENCE ON RECENT TRENDS IN INFORMATION TECHNOLOGY (ICRTIT), 2013, : 657 - 662
  • [38] An Energy-Aware Mapping Algorithm for Mesh-based Network-on-Chip Architectures
    Sun, Jin
    Zhang, Yi
    [J]. PROCEEDINGS OF 2017 IEEE INTERNATIONAL CONFERENCE ON PROGRESS IN INFORMATICS AND COMPUTING (PIC 2017), 2017, : 357 - 361
  • [39] Core/Task Associations For Efficient Application Implementation On Network-On-Chip
    Bougherara, Maamar
    Nedjah, Nadia
    Bennouar, Djamel
    Rahmoun, Rym
    Sadok, Amel
    Mourelle, Luiza de Macedo
    [J]. 2018 INTERNATIONAL CONFERENCE ON COMPUTER AND APPLICATIONS (ICCA), 2018, : 18 - 22
  • [40] Fault Tolerant Mesh based Network-on-Chip Architecture
    Chatterjee, Navonil
    Chattopadhyay, Santanu
    [J]. 2015 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), 2015, : 417 - 420