A Fast FPGA-Based Classification of Application Protocols Optimized Using Cartesian GP

This paper deals with design of an application protocol classifier intended for high speed networks operating at 100 Gbps. Because a very low latency is the main design constraint, the classifier is constructed as a combinational circuit in a field programmable gate array. The classification is performed using the first packet carrying the application payload. In order to further reduce the latency, the circuit is optimized by Cartesian genetic programming Using a real network data, we demonstrated viability of our approach in task of a very fast classification of three application protocols (HTTP, SMTP, SSH).