High-level symbolic simulation for automatic model extraction

被引：2
|
作者：
Ouchet, Florent [1 ]
Borrione, Dominique [1 ]
Morin-Allory, Katell [1 ]
Pierre, Laurence [1 ]
机构：
[1] UJF, CNRS, Grenoble INP, TIMA Lab, Grenoble, France
来源：
PROCEEDINGS OF THE 2009 IEEE SYMPOSIUM ON DESIGN AND DIAGNOSTICS OF ELECTRONIC CIRCUITS AND SYSTEMS | 2009年
关键词：
Hardware design language; simulation software; circuit simulation;
D O I：
10.1109/DDECS.2009.5012132
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
This paper describes VSYML, a symbolic simulator that extracts formal models from VHDL descriptions. The generated models are adequate to formal reasoning in various frameworks. VSYML is a reimplementation of its ancestor Theosim; it brings various improvements e.g., with regard to arrays and other complex data types.
引用
收藏
页码：218 / 221
页数：4
相关论文
共 50 条
  • [21] Parallelity in high-level simulation architectures
    Jugel, ML
    Sydow, A
    TRANSACTIONS OF THE SOCIETY FOR COMPUTER SIMULATION INTERNATIONAL, 1998, 15 (03): : 101 - 103
  • [22] Automatic Model Refinement of GmC Integrators for High-Level Simulation of Continuous-Time Sigma-Delta Modulators
    Vasilevski, Michel
    Aboushady, Hassan
    Louerat, Marie-Minerve
    ISCAS: 2009 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-5, 2009, : 2769 - 2772
  • [23] A model and an algorithm for VHDL high-level and hierarchical simulation with debug function
    Bian, JN
    Lu, F
    Wan, B
    Su, M
    FOURTH INTERNATIONAL CONFERENCE ON COMPUTER-AIDED DESIGN AND COMPUTER GRAPHICS, 1996, 2644 : 791 - 796
  • [24] NeuroLISP: High-level symbolic programming with attractor neural networks
    Davis, Gregory P.
    Katz, Garrett E.
    Gentili, Rodolphe J.
    Reggia, James A.
    NEURAL NETWORKS, 2022, 146 : 200 - 219
  • [25] Enhancing topological ATPG with high-level information and symbolic techniques
    Corno, F
    Patel, JH
    Rudnick, EM
    Reorda, MS
    Vietti, R
    INTERNATIONAL CONFERENCE ON COMPUTER DESIGN: VLSI IN COMPUTERS AND PROCESSORS, PROCEEDINGS, 1998, : 504 - 509
  • [26] Finite symbolic reachability graphs for high-level Petri nets
    Hameurlain, N
    Sibertin-Blanc, C
    ASIA PACIFIC SOFTWARE ENGINEERING CONFERENCE AND INTERNATIONAL COMPUTER SCIENCE CONFERENCE, PROCEEDINGS, 1997, : 150 - 159
  • [27] A New Framework for High-level Feature Extraction
    Gao, Zan
    Nan, Xiaoming
    Liu, Tao
    Zhao, Zhicheng
    Cai, Anni
    ICIEA: 2009 4TH IEEE CONFERENCE ON INDUSTRIAL ELECTRONICS AND APPLICATIONS, VOLS 1-6, 2009, : 2109 - 2113
  • [28] Automatic generation of high-level contact state space
    Xiao, J
    Ji, XR
    INTERNATIONAL JOURNAL OF ROBOTICS RESEARCH, 2001, 20 (07): : 584 - 606
  • [29] Automatic Implementation of Arithmetic Functions in High-Level Synthesis
    Ge, Liangwei
    Chen, Song
    Yoshimura, Takeshi
    2008 9TH INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED-CIRCUIT TECHNOLOGY, VOLS 1-4, 2008, : 2341 - 2344
  • [30] Automatic cache partitioning method for high-level synthesis
    Jones, Bryant
    Hanna, Darrin M.
    MICROPROCESSORS AND MICROSYSTEMS, 2019, 67 : 71 - 81
12345