An on-chip CDMA communication network

An on-chip packet-switched communication network which applies Code-Division Multiple Access (CDMA) technique has been developed and implemented in Register-Transfer Level (RTL) using VHDL. In order to support Globally-Asynchronous Locally-Synchronous (GALS) communication scheme, the proposed CDMA on-chip network combines both synchronous and asynchronous circuits together. In a packet-switched Network-on-Chip (NoC) which applies point-to-point connection scheme, the data transfer latency varies largely if the packets are transferred to different destinations or to a same destination through different routes in the network. The proposed CDMA NoC can make the data transfer latency become a constant value by multiplexing the data transfers in code domain instead of in time domain. Therefore, the data transfer latency can be guaranteed in the proposed CDMA network by avoiding communication media sharing in time domain.