Microstructural investigation of through-silicon via fabrication by pulse-reverse electroplating for high density nanoelectronics

被引:0
|
作者
Lin, Nay [1 ]
Miao, Jianmin [1 ]
Preisser, Robert [2 ]
机构
[1] Nanyang Technol Univ, Sch Mech & Aerosp Engn, Singapore 639798, Singapore
[2] Atotech USA Inc, Coll Nanoscale Sci & Engn, Albany, NY 12203 USA
关键词
TSV; copper; pulse reverse electroplating; DRIE;
D O I
10.1504/IJNT.2014.059821
中图分类号
TB3 [工程材料学];
学科分类号
0805 ; 080502 ;
摘要
In this paper, fabrication of through-silicon vias (TSV) with different diameters ranging from 60 mu m to 150 mu m is reported. It was observed that at the low current density of 20 mA/cm(2), all the through-holes with different diameters are filled with copper without voids and pores. At higher current density of 40 mA/cm(2), however, the pillars with diameters bigger than 100 mu m tend to have voids at the middle portion of pillars. Focused ion beam (FIB) examination of the copper pillars fabricated with low current density reveals the difference in grain size and internal structure of the grain along the length of the pillar. Current-potential characters of solution were studied for the electrolyte bath used in the process. It shows the limiting current density around 40-60 mA/cm(2). The microstructures of TSV fabricated at low and high current densities are investigated and it shows that high current density produces porous copper with void at the core of TSV.
引用
收藏
页码:178 / 189
页数:12
相关论文
共 50 条
  • [21] Integration of high aspect ratio tapered silicon via for through-silicon interconnection
    Ranganathan, N.
    Ebin, Liao
    Linn, Linn
    Vincent, Lee Wen Sheng
    Navas, O. K.
    Kripesh, V.
    Balasubramanian, N.
    58TH ELECTRONIC COMPONENTS & TECHNOLOGY CONFERENCE, PROCEEDINGS, 2008, : 859 - 865
  • [22] Composition controlling of Co-Ni and Fe-Co alloys using pulse-reverse electroplating through means of experimental strategies
    Bai, A
    Hu, CC
    ELECTROCHIMICA ACTA, 2005, 50 (06) : 1335 - 1345
  • [23] Modeling, Fabrication, and Characterization of 3-D Capacitor Embedded in Through-Silicon Via
    Lin, Ye
    Tan, Chuan Seng
    IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY, 2018, 8 (09): : 1524 - 1532
  • [24] A high-pass filter based on through-silicon via (TSV)
    Wang, Fengjuan
    Huang, Jia
    Yu, Ningmei
    IEICE ELECTRONICS EXPRESS, 2019, 16 (10) : 1 - 3
  • [25] High-Frequency Through-Silicon Via (TSV) Failure Analysis
    Kim, Joohee
    Cho, Jonghyun
    Pak, Jun So
    Kim, Joungho
    Yook, Jong-Min
    Kim, Jun Chul
    2011 IEEE 20TH CONFERENCE ON ELECTRICAL PERFORMANCE OF ELECTRONIC PACKAGING AND SYSTEMS (EPEPS), 2011, : 243 - 246
  • [26] High rate deep Si etching for through-silicon via applications
    Sakai, Itsuko
    Sakurai, Noriko
    Ohiwa, Tokuhisa
    JOURNAL OF VACUUM SCIENCE & TECHNOLOGY A, 2011, 29 (02):
  • [27] Fabrication and electrical characterization of high aspect ratio poly-silicon filled through-silicon vias
    Dixit, Pradeep
    Vehmas, Tapani
    Vahanen, Sami
    Monnoyer, Philippe
    Henttinen, Kimmo
    JOURNAL OF MICROMECHANICS AND MICROENGINEERING, 2012, 22 (05)
  • [28] High Density Through Silicon Via (TSV)
    Rimskog, Magnus
    Bauer, Tomas
    DTIP 2008: SYMPOSIUM ON DESIGN, TEST, INTEGRATION AND PACKAGING OF MEMS/MOEMS, 2008, : 105 - 108
  • [29] Modeling of Through-silicon Via (TSV) with an hmbedded High-density Metal-insulator-metal (MIM) Capacitor
    Cho, Kyunjun
    Kim, Youngwoo
    Kim, Subin
    Park, Gapyeol
    Son, Kyungjune
    Park, Hyunwook
    Kim, Seongguk
    Choi, Sumin
    Kim, Dong-Hyun
    Kim, Joungho
    2018 IEEE ELECTRICAL DESIGN OF ADVANCED PACKAGING AND SYSTEMS SYMPOSIUM (EDAPS 2018), 2018,
  • [30] A Study on Through-Silicon-via Using Tri-Block Copolymer and Pulse Electroplating
    Son, Hwa-Jin
    Kim, Tae-Yoo
    Suh, Su-Jeong
    JOURNAL OF NANOSCIENCE AND NANOTECHNOLOGY, 2016, 16 (08) : 8396 - 8401