A Study on Through-Silicon-via Using Tri-Block Copolymer and Pulse Electroplating

In recent years, the integration density of semiconductor devices has improved, resulting in the development of multi-chip packages manufactured by through-silicon-via (TSV) methods. 3D chip integration using TSV copper is considered to be one of the most advanced technologies over the entire range of 3D packaging technologies. However, defects such as void and seam are easily formed during copper electroplating for TSVs. In an attempt to obtain high-performance devices, defects should be minimized because they can be serious problems including signal noise, mechanical cracking, and poor reliability. In this paper, void-free filling was achieved by adding polyethylene oxide-polypropylene oxide-polyethylene oxide (EPE-2000) as a suppressor and bis(3-sulfopropyl)disulfide (SPS) as an accelerator the electroplating bath. Cyclic voltammetry (CV) measurements were carried out to investigate the characteristics of the Cu deposition additive. Electro-deposition was performed by combining tri-block copolymer EPE-2000 and SPS. The TSV filling behavior was then confirmed by assessing the on-reverse waveform and frequency. The results indicated that void-free TSV filling can be achieved using EPE-2000 and SPS. The effect of the additive on the blind-via filling during pulse electro-deposition was investigated by capturing cross-sectional images using an optical microscope (OM) and a scanning electron microscope (SEM).