Post-silicon timing yield enhancement using dual-mode elements

被引：1

作者：

Kim, W. ^{[1
]}

Park, H. S. ^{[1
]}

Kim, Y. H. ^{[1
]}

机构：

[1] POSTECH, Div Elect & Comp Engn, Pohang 790784, Gyungbuk, South Korea

来源：

ELECTRONICS LETTERS | 2009年 / 45卷 / 16期

关键词：

D O I：

10.1049/el.2009.1200

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

A simple but effective technique for timing yield enhancement is presented. The proposed technique tunes circuit timing using dual-mode elements, which are special logic gates that can change delay leakage characteristics at the post-silicon level. In experiments using the ISCAS-85 benchmarks, the proposed technique reduced the timing failure rate by 59.52% on average.

引用

页码：827 / 828

页数：2

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