共 50 条
- [1] A system level exploration platform and methodology for network applications based on configurable processors [J]. DESIGN, AUTOMATION AND TEST IN EUROPE CONFERENCE AND EXHIBITION, VOLS 1 AND 2, PROCEEDINGS, 2004, : 364 - 369
- [2] System-Level Security for Network Processors with Hardware Monitors [J]. 2014 51ST ACM/EDAC/IEEE DESIGN AUTOMATION CONFERENCE (DAC), 2014,
- [3] NetVP: A System-Level NETwork Virtual Platform for Network Accelerator Development [J]. 2012 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS 2012), 2012, : 249 - 252
- [4] System-level exploration with SpecSyn [J]. 1998 DESIGN AUTOMATION CONFERENCE, PROCEEDINGS, 1998, : 812 - 817
- [5] A System-Level Network Virtual Platform for IPsec Processor Development [J]. IEICE TRANSACTIONS ON INFORMATION AND SYSTEMS, 2013, E96D (05): : 1095 - 1104
- [6] System-level modeling of DSP and embedded processors [J]. CONFERENCE RECORD OF THE THIRTY-SECOND ASILOMAR CONFERENCE ON SIGNALS, SYSTEMS & COMPUTERS, VOLS 1 AND 2, 1998, : 1730 - 1734
- [8] A system-level Performance Evaluation Methodology for Network Processors Based on Network Calculus Analytical Modehng [J]. IEEE COMPUTER SOCIETY ANNUAL SYMPOSIUM ON VLSI, PROCEEDINGS: EMERGING VLSI TECHNOLOGIES AND ARCHITECTURES, 2007, : 265 - +
- [9] A system-level EMC Technical Support Platform for network-based computers [J]. 2008 ASIA-PACIFIC SYMPOSIUM ON ELECTROMAGNETIC COMPATIBILITY AND 19TH INTERNATIONAL ZURICH SYMPOSIUM ON ELECTROMAGNETIC COMPATIBILITY, VOLS 1 AND 2, 2008, : 642 - +
- [10] System-level exploration tools for MPSoC designs [J]. 43rd Design Automation Conference, Proceedings 2006, 2006, : 286 - 287