A 12 Bit IF Sampling Pipelined ADC in 0.18um BiCMOS

被引：0
|
作者：
Li, Liang [1 ]
Fu, Dongbing [2 ]
Xu, Mingyuan [1 ]
Huang, Xingfa [1 ]
机构：
[1] Sci & Technol Analog Integrated Circuit Lab, Chongqing 400060, Peoples R China
[2] CETC, SISC, Chongqing 400060, Peoples R China
来源：
PROCEEDINGS OF THE 3RD INTERNATIONAL CONFERENCE ON MATERIAL, MECHANICAL AND MANUFACTURING ENGINEERING | 2015年 / 27卷
关键词：
switched capacitor; IF Sampling; input buffer; BiCMOS;
D O I：
暂无
中图分类号：
T [工业技术];
学科分类号：
08 ;
摘要：
In this paper, a 12 bit 500MS/s IF Sampling ADC is described. The ADC has an integrated input buffer with a new linearization technique that improves its distortion. Eight pipeline stages with fully differential switched capacitor architecture follow the input buffer. Each of stage of the pipeline, excluding the last, consists of a low resolution flash ADC connected to a switched capacitor DAC and interstage residue amplifier(MDAC). A 0.18 mu m BiCMOS process with 1.8V analog power supply is used in the design. This ADC achieves an SNR of 65dB and an SFDR of 82dB for sampling analog input frequencies up to 250MHz
引用
收藏
页码：926 / 929
页数：4
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