Substrate noise-aware floorplanning for mixed-signal SOCs

被引：0

作者：

Jeske, M ^{[1
]}

Blakiewicz, G ^{[1
]}

Chrzanowska-Jeske, M ^{[1
]}

Wang, B ^{[1
]}

机构：

[1] Portland State Univ, Dept Elect & Comp Engn, Portland, OR 97207 USA

来源：

2004 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOL 2, PROCEEDINGS | 2004年

关键词：

D O I：

暂无

中图分类号：

TP18 [人工智能理论];

学科分类号：

081104 ; 0812 ; 0835 ; 1405 ;

摘要：

To reduce substrate-coupling noise in mixed-signal SOCs, we propose a new floorplanning method that considers substrate-coupling noise and adjusts placement of digital and analog blocks to reduce the influence of digital switching on the performance of sensitive analog circuits. A simple model of the influence of distance between blocks on distortion is used to compute a distortion number for a layout. As a result of noise optimization during floorplanning, the distortion numbers for MCNC benchmark-based circuits are significantly reduced compared to floorplans generated without optimizing for noise. Experimental results are very encouraging.

引用

页码：445 / 448

页数：4

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