Mask specification for wafer process optimization

被引：0

作者：

Chen, Lin ^{[1
]}

Freiberger, Phil ^{[1
]}

Farnsworth, Jeff ^{[1
]}

Stritsman, Ruth ^{[1
]}

Rodrigues, Richard P. ^{[1
]}

机构：

[1] Intel Corp, SC2-12,2200 Miss Coll Blvd, Santa Clara, CA 95052 USA

来源：

PHOTOMASK TECHNOLOGY 2006, PTS 1 AND 2 | 2006年 / 6349卷

关键词：

mask integration; specification;

D O I：

10.1117/12.686610

中图分类号：

O43 [光学];

学科分类号：

070207 ; 0803 ;

摘要：

Mask specification has been playing ever-increasing role for wafer process optimization with tightening design rule. It is very critical to optimize specifications and sampling sizes to ensure quality as well as minimize cost and TPT for high volume manufacturing. In this paper, key parameters for mask specification affecting wafer litho process window will be discussed. Examples of how to derive key mask specification based on the litho process margin will be examined. The mask CD targeting control and plate to plate CD variation reduction strategy will be discussed.

引用

页数：11

共 50 条

[1] Application of a wafer development process to mask making
Lee, G
Berger, C
Bürgel, C
Feicke, A
Cantrell, R
Tschinkl, M
[J]. PHOTOMASK AND NEXT-GENERATION LITHOGRAPHY MASK TECHNOLOGY XII, PTS 1 AND 2, 2005, 5853 : 445 - 453
[2] Strategy optimization for mask rule check in wafer fab
Yang, Chuen Huei
Lin, Shaina
Lin, Roger
Wang, Alice
Lee, Rachel
Deng, Erwin
[J]. PHOTOMASK JAPAN 2015: PHOTOMASK AND NEXT-GENERATION LITHOGRAPHY MASK TECHNOLOGY XXII, 2015, 9658
[3] Source and mask optimization for stability of reticle and wafer stages
Shen, Hao
Zhang, Libin
Rui, Dinghai
Liu, Ge
Su, Yajuan
Wei, Yayi
Fang, Ming
[J]. OPTICS EXPRESS, 2024, 32 (19): : 33603 - 33617
[4] SOI wafer flow process for stencil mask fabrication
Butschke, J
Ehrmann, A
Höfflinger, B
Irmscher, M
Käsmaier, R
Letzkus, F
Löschner, H
Mathuni, J
Reuter, C
Schomburg, C
Springer, R
[J]. MICROELECTRONIC ENGINEERING, 1999, 46 (1-4) : 473 - 476
[5] An advanced modeling approach for mask and wafer process simulation
Karakas, Ahmet
Elsen, Erich
Torunoglu, Ilhami
Andrus, Curtis
[J]. PHOTOMASK TECHNOLOGY 2010, 2010, 7823
[6] Process optimization on mask fabrication
Sakurai, H
Itoh, M
Kumagae, A
Anze, H
Abe, T
Higashikawa, I
[J]. PHOTOMASK AND X-RAY MASK TECHNOLOGY V, 1998, 3412 : 183 - 189
[7] PN and SOI wafer flow process for stencil mask fabrication
Butschke, J
Ehrmann, A
Haugeneder, E
Irmscher, M
Käsmaier, R
Kragler, K
Letzkus, F
Löschner, H
Mathuni, J
Rangelow, IW
Reuter, C
Shi, F
Springer, R
[J]. 15TH EUROPEAN CONFERENCE ON MASK TECHNOLOGY FOR INTEGRATED CIRCUITS AND MICROCOMPONENTS '98, 1999, 3665 : 20 - 29
[8] Single mask wafer overcoat process using photodefinable polyimide
Hall, S
Schuckert, CC
[J]. SOLID STATE TECHNOLOGY, 1999, 42 (10) : 95 - 96
[9] Mask absorber, mask tone, and wafer process impact on resist line-edge-roughness
Ohtomi, Eisuke
Philipsen, Vicky
Welling, Ulrich
Melvin III, Lawrence S.
Takahata, Yosuke
Tanaka, Yusuke
De Simone, Danilo
[J]. JOURNAL OF MICRO-NANOPATTERNING MATERIALS AND METROLOGY-JM3, 2023, 22 (04):
[10] Mask critical dimension specification considering process sensitivity of mask error in extreme ultraviolet lithography
Huh, Sungmin
Kim, Hoon
Jang, Ilyong
Cho, Sung-Yong
Kim, Dongwan
Lee, Jeung-Woo
Choi, Seoungwoon
Han, Woosung
[J]. JAPANESE JOURNAL OF APPLIED PHYSICS PART 1-REGULAR PAPERS BRIEF COMMUNICATIONS & REVIEW PAPERS, 2007, 46 (9B): : 6145 - 6149

← 1 2 3 4 5 →