Mask specification for wafer process optimization

被引：0
|
作者：
Chen, Lin [1 ]
Freiberger, Phil [1 ]
Farnsworth, Jeff [1 ]
Stritsman, Ruth [1 ]
Rodrigues, Richard P. [1 ]
机构：
[1] Intel Corp, SC2-12,2200 Miss Coll Blvd, Santa Clara, CA 95052 USA
来源：
PHOTOMASK TECHNOLOGY 2006, PTS 1 AND 2 | 2006年 / 6349卷
关键词：
mask integration; specification;
D O I：
10.1117/12.686610
中图分类号：
O43 [光学];
学科分类号：
070207 ; 0803 ;
摘要：
Mask specification has been playing ever-increasing role for wafer process optimization with tightening design rule. It is very critical to optimize specifications and sampling sizes to ensure quality as well as minimize cost and TPT for high volume manufacturing. In this paper, key parameters for mask specification affecting wafer litho process window will be discussed. Examples of how to derive key mask specification based on the litho process margin will be examined. The mask CD targeting control and plate to plate CD variation reduction strategy will be discussed.
引用
收藏
页数：11
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