A NEW HIGH-LEVEL METHODOLOGY FOR PROGRAMMING FPGA-BASED SMART CAMERA

被引:2
|
作者
Roudel, Nicolas [1 ]
Berry, Francois [1 ]
Serot, Jocelyn [1 ]
Eck, Laurent [2 ]
机构
[1] Univ Blaise Pascal, UMR 6602, CNRS, 24 Ave Landais, F-63177 Clermont Ferrand, France
[2] CEA, LIST, F-92265 Fontenay Aux Roses, France
关键词
Soft-core; methodology; smart camera; heterogeneous platforms; CAL; processing elements;
D O I
10.1109/DSD.2010.68
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
Due to the various devices composing a smart camera system, various languages have to be known by the designer (like HDL and C/C++). Most of vision applications designers are software program-tiers and do not have a good knowledge of HDLs (VHDL). This paper presents a new high-level methodology for implementing vision applications on smart camera platforms. This methodology is based on a soft-core approach to manage the whole system and a dataflow (actor-oriented) language to design the processing elements. We discuss in particular interfacing constraints.
引用
收藏
页码:573 / 578
页数:6
相关论文
共 50 条
  • [31] Modelling macromodules for high-level dynamic power estimation of FPGA-based digital designs
    Reimer, Axel
    Schulz, Arne
    Nebel, Wolfgang
    ISLPED '06: Proceedings of the 2006 International Symposium on Low Power Electronics and Design, 2006, : 151 - 154
  • [32] HAPE: A high-level area-power estimation framework for FPGA-based accelerators
    Makni, Mariem
    Niar, Smail
    Baklouti, Mouna
    Abid, Mohamed
    MICROPROCESSORS AND MICROSYSTEMS, 2018, 63 : 11 - 27
  • [33] High-Level Languages and Floating-Point Arithmetic for FPGA-Based CFD Simulations
    Sanchez-Roman, Diego
    Sutter, Gustavo
    Lopez-Buedo, Sergio
    Gonzalez, Ivan
    Gomez-Arribas, Francisco J.
    Aracil, Javier
    Palacios, Francisco
    IEEE DESIGN & TEST OF COMPUTERS, 2011, 28 (04): : 28 - 36
  • [34] Lin-Analyzer: A High-level Performance Analysis Tool for FPGA-based Accelerators
    Zhong, Guanwen
    Prakash, Alok
    Liang, Yun
    Mitra, Tulika
    Niar, Smail
    2016 ACM/EDAC/IEEE DESIGN AUTOMATION CONFERENCE (DAC), 2016,
  • [35] High-Level Synthesis Hardware Design for FPGA-Based Accelerators: Models, Methodologies, and Frameworks
    Molina, Romina Soledad
    Gil-Costa, Veronica
    Crespo, Maria Liz
    Ramponi, Giovanni
    IEEE ACCESS, 2022, 10 : 90429 - 90455
  • [36] High-level FPGA Programming through Mapping Process Networks to FPGA Resources
    Mayer-Lindenberg, Fritz
    2009 INTERNATIONAL CONFERENCE ON RECONFIGURABLE COMPUTING AND FPGAS, 2009, : 302 - 307
  • [37] FPGA high-level design methodology comes into its own
    Kresta, D
    Johnson, T
    ELECTRONIC DESIGN, 1999, 47 (12) : 57 - +
  • [38] Binary Division Power Models for High-Level Power Estimation of FPGA-Based DSP Circuits
    Jovanovic, Bojan
    Jevtic, Ruzica
    Carreras, Carlos
    IEEE TRANSACTIONS ON INDUSTRIAL INFORMATICS, 2014, 10 (01) : 393 - 398
  • [39] Accelerating FPGA-Based Wi-Fi Transceiver Design and Prototyping by High-Level Synthesis
    Havinga, Thijs
    Jiao, Xianjun
    Liu, Wei
    Moerman, Ingrid
    2023 IEEE 31ST ANNUAL INTERNATIONAL SYMPOSIUM ON FIELD-PROGRAMMABLE CUSTOM COMPUTING MACHINES, FCCM, 2023, : 219 - 219
  • [40] Toward a smart camera for fast high-level structure extraction
    de Lima, Roberto
    Martinez-Carranza, Jose
    Morales-Reyes, Alicia
    Mayol-Cuevas, Walterio
    JOURNAL OF REAL-TIME IMAGE PROCESSING, 2018, 14 (03) : 685 - 699