Fully source-coupled logic based multiple-valued VLSI

被引：0
|
作者：
Ike, T [1 ]
Hanyu, T [1 ]
Kameyama, M [1 ]
机构：
[1] Tohoku Univ, Dept Comp & Math Sci, Grad Sch Informat Sci, Sendai, Miyagi 9808579, Japan
来源：
ISMVL 2002: 32ND IEEE INTERNATIONAL SYMPOSIUM ON MULTIPLE-VALUED LOGIC, PROCEEDINGS | 2002年
关键词：
D O I：
暂无
中图分类号：
TP18 [人工智能理论];
学科分类号：
081104 ; 0812 ; 0835 ; 1405 ;
摘要：
A novel source-coupled logic (SCL) style using multiple-valued signals, called multiple-valued source-coupled logic (MVSCL), which operates with an input voltage swing of about 0.3V is proposed for high-speed and low-power VLSI systems. A multiple-valued comparator which is a key component, is realized by using differential-pair circuits (DPCs), so that its power dissipation can be greatly reduced while maintaining high-speed switching. Moreover, the current-source control allows steady current flow to cut off when the circuit is not active, thereby saving power dissipation. A 54x54-bit signed-digit multiplier based on MVSCL is designed in a 0.35-mum CMOS technology, and its performance is superior to both corresponding binary. static CMOS and multiple-valued current-mode (MVCM) implementation.
引用
收藏
页码：270 / 275
页数：6
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