Application of submodeling technique to transient drop impact analysis of board-level stacked die packages

被引:0
|
作者
Hsu, Hsiang-Chen
Hsu, Yu-Chia
Lee, Hui-Yu
Yeh, Chang-Lin
Lai, Yi-Shao
机构
关键词
submodeling technique; support excitation scheme; pulse-controlled board-level drop test; stacked-die; cut boundary;
D O I
暂无
中图分类号
T [工业技术];
学科分类号
08 ;
摘要
The objective of this research is to investigate the effects of board-level drop test based on the support excitation scheme incoporated with the submodel technique for stacked-die packages. This paper also demonstrates the transient dynamic response for lead-free SAC405 (95.5Sn4Ag0.5Cu) solder balls subject to JEDEC pulse-controlled board-level drop test standard JESD22-B110A Condition B[1]. To evaluate the structure of the interested area, a strip model sliced from the full test vehicle is used in this research. In addition, the submodel region is particularly chosen with strip model by performing the cut boundary interpolation. The envelope of equivalent stress for the outermost solder joint off the end of the strip model is plot to show the potential solder failure mode and mechanism. The cut boundary of submodel is verified and the mesh density of submodel is examined. For a refinery mesh of submodel, parametric studies are carried out to study the reliability of the outermost solder joint, and the results are summarized as design rules for the development of stacked-die packages.
引用
收藏
页码:412 / 418
页数:7
相关论文
共 50 条
  • [1] Finite element analysis of dynamic drop impact of board-level stacked-die packages using submodeling technique
    Hsu, Hsiang-Chen
    Hsu, Yu-Chia
    Lee, Hui-Yu
    Yeh, Chang-Lin
    Lai, Yi-Shao
    Fu, Shen-Li
    2006 INTERNATIONAL CONFERENCE ON ELECTRONIC MATERIALS AND PACKAGING, VOLS 1-3, 2006, : 398 - 405
  • [2] Transient submodeling analysis for board-level drop tests of electronic packages
    Tsai, Tsung-Yueh
    Yeh, Chang-Lin
    Lai, Yi-Shao
    Chen, Rong-Sheng
    IEEE TRANSACTIONS ON ELECTRONICS PACKAGING MANUFACTURING, 2007, 30 (01): : 54 - 62
  • [3] Dynamics of board-level drop impact
    Wong, EH
    JOURNAL OF ELECTRONIC PACKAGING, 2005, 127 (03) : 200 - 207
  • [4] Failure Mechanism of Stacked CSP Module under Board-Level Drop Impact
    Narravula, Vikram
    Chen, Cheng-fu
    Peterson, Daniel C.
    2009 IEEE 59TH ELECTRONIC COMPONENTS AND TECHNOLOGY CONFERENCE, VOLS 1-4, 2009, : 2039 - 2045
  • [5] Transient analysis of drop responses of board-level electronic packages using response spectra incorporated with modal superposition
    Yeh, Chang-Lin
    Tsai, Tsung-Yueh
    Lai, Yi-Shao
    MICROELECTRONICS RELIABILITY, 2007, 47 (12) : 2188 - 2196
  • [6] Transient analysis of board-level drop response of lead-free chip-scale packages with experimental verifications
    Yeh, CL
    Lai, YS
    6TH ELECTRONICS PACKAGING TECHNOLOGY CONFERENCE, PROCEEDINGS (EPTC 2004), 2004, : 695 - 700
  • [7] Study on the board-level drop test of the stacked memory device by FEA
    Pang, Junwen
    Wang, Jun
    Zhao, Liyou
    2014 15TH INTERNATIONAL CONFERENCE ON ELECTRONIC PACKAGING TECHNOLOGY (ICEPT), 2014, : 724 - 727
  • [8] Support excitation scheme for transient analysis of JEDEC board-level drop test
    Yeh, CL
    Lai, YS
    MICROELECTRONICS RELIABILITY, 2006, 46 (2-4) : 626 - 636
  • [9] INVESTIGATION OF BOARD-LEVEL AND PACKAGE-LEVEL DROP RELIABILITY OF RF MEMS PACKAGES
    Sun, Li
    DeReus, Dana
    Cunningham, Shawn
    Morris, Art
    IMCE2009: PROCEEDINGS OF THE ASME INTERNATIONAL MECHANICAL ENGINEERING CONGRESS AND EXPOSITION, VOL 5, 2010, : 225 - 230
  • [10] A numerical study of board-level stacked-die packages under coupled power and thermal cycling test conditions
    Wang, Tong Hong
    Lee, Chang-Chi
    Wang, Ching-Chun
    Lai, Yi-Shao
    2006 INTERNATIONAL MICROSYSTEMS, PACKAGING, ASSEMBLY CONFERENCE TAIWAN (IMPACT), PROCEEDINGS, 2006, : 123 - +