ProperTEST: A portable parallel test generator for sequential circuits

被引:1
|
作者
Ramkumar, B
Banerjee, P
机构
[1] UNIV IOWA,DEPT ELECT & COMP ENGN,IOWA CITY,IA 52242
[2] NORTHWESTERN UNIV,DEPT ELECT & COMP ENGN,EVANSTON,IL 60208
基金
美国国家科学基金会; 美国国家航空航天局;
关键词
D O I
10.1109/43.631220
中图分类号
TP3 [计算技术、计算机技术];
学科分类号
0812 ;
摘要
Parallel algorithms developed for CAD problems today suffer from two important drawbacks, First, they are machine specific, and tend to perform poorly on architectures other than the one for they were designed, Second, the quality of results degrades significantly during parallel execution. In this paper, we address these two problems for an important CAD application: test generation for sequential circuits, We have developed a new parallel test generator, ProperTEST, that is portable across a range of MIMD parallel architectures, This work is part of the ProperCAD project which aims to develop CAD algorithms that run unchanged on shared and nonshared memory machines, We present performance data for ProperTEST on ISCAS 89 sequential circuits on a Sequent Symmetry, an InteI i860 hypercube, an NCUBE/2 hypercube, a network of Sun workstations, and an Encore Multimax. Parallel processing can also be used to improve on the fault coverage possible on one processor in a given amount of time, This was not possible in earlier approaches due to search anomalies, Using ProperTEST, we provide results on ISCAS 89 benchmark programs demonstrating the improvements in fault coverage as the number of processors is increased.
引用
收藏
页码:555 / 569
页数:15
相关论文
共 50 条
  • [31] Diagnostic test pattern generation for sequential circuits
    Hartanto, I
    Boppana, V
    Patel, JH
    Fuchs, WK
    [J]. 15TH IEEE VLSI TEST SYMPOSIUM, PROCEEDINGS, 1997, : 196 - 202
  • [32] FsmTest: Functional test generation for sequential circuits
    Buonanno, G
    Fummi, F
    Sciuto, D
    Lombardi, F
    [J]. INTEGRATION-THE VLSI JOURNAL, 1996, 20 (03) : 303 - 325
  • [33] A new method of test generation for sequential circuits
    Hou, Yanli
    Zhao, Chunhui
    Liao, Yanping
    [J]. 2006 INTERNATIONAL CONFERENCE ON COMMUNICATIONS, CIRCUITS AND SYSTEMS PROCEEDINGS, VOLS 1-4: VOL 1: SIGNAL PROCESSING, 2006, : 2181 - 2185
  • [34] On improving static test compaction for sequential circuits
    Guo, R
    Pomeranz, I
    Reddy, SM
    [J]. VLSI DESIGN 2001: FOURTEENTH INTERNATIONAL CONFERENCE ON VLSI DESIGN, 2001, : 111 - 116
  • [35] ON SERIES-TO-PARALLEL TRANSFORMATION OF LINEAR SEQUENTIAL CIRCUITS
    GILL, A
    [J]. IEEE TRANSACTIONS ON ELECTRONIC COMPUTERS, 1966, EC15 (01): : 107 - +
  • [36] Test compaction for synchronous sequential circuits by test sequence recycling
    Pomeranz, I
    Reddy, SM
    [J]. PROCEEDINGS OF THE 8TH GREAT LAKES SYMPOSIUM ON VLSI, 1998, : 216 - 221
  • [37] Signature analysis for test responses of sequential circuits
    Stroele, AP
    [J]. VLSI DESIGN, 1999, 10 (02) : 127 - 141
  • [38] Test pattern generator for hybrid testing of combinational circuits
    De Caro, D
    Mazzocca, N
    Napoli, E
    Saggese, GP
    Strollo, AGM
    [J]. ICECS 2001: 8TH IEEE INTERNATIONAL CONFERENCE ON ELECTRONICS, CIRCUITS AND SYSTEMS, VOLS I-III, CONFERENCE PROCEEDINGS, 2001, : 745 - 748
  • [39] Next Generation Test Generator (NGTG) for analog circuits
    Venetsky, L
    Singer, S
    [J]. AUTOTESTCON '97 - IEEE SYSTEMS READINESS TECHNOLOGY CONFERENCE, 1997 IEEE AUTOTESTCON PROCEEDINGS, 1997, : 113 - 120
  • [40] Next Generation Test Generator (NGTG) for digital circuits
    Singer, S
    Vanetsky, L
    [J]. AUTOTESTCON '97 - IEEE SYSTEMS READINESS TECHNOLOGY CONFERENCE, 1997 IEEE AUTOTESTCON PROCEEDINGS, 1997, : 105 - 112