Developing a systematic approach to metal gates and high-k dielectrics in future-generation CMOS

被引:0
|
作者
Majhi, Prashant [1 ]
Wen, Huang-Chun [1 ]
Alshareef, Husam [1 ]
Harris, H. Rusty [1 ]
Luan, Hongfa [1 ]
Choi, Kisik [1 ]
Park, C. S. [1 ]
Song, Seung-Chul [1 ]
Lee, Byoung Hun [1 ]
Jammy, Raj [1 ]
机构
[1] SEMATECH, Austin, TX 78741 USA
来源
MICRO | 2006年 / 24卷 / 04期
关键词
D O I
暂无
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
Sematech researchers present a terraced-oxide method for extracting the effective work function of metal gates in an effort to integrate metal gates and high-k dielectrics in CMOS devices.
引用
收藏
页码:25 / 32
页数:8
相关论文
共 50 条
  • [21] Approaches to CMOS integration of epitaxial gadolinium oxide high-K dielectrics
    Gottlob, H. D. B.
    Echtermeyer, T.
    Mollenhauer, T.
    Schmidt, M.
    Efavi, J. K.
    Wahlbrink, T.
    Lemme, M. C.
    Kurz, H.
    Endres, R.
    Stefanov, Y.
    Schwalke, U.
    ESSDERC 2006: PROCEEDINGS OF THE 36TH EUROPEAN SOLID-STATE DEVICE RESEARCH CONFERENCE, 2006, : 150 - +
  • [22] Normal and Reverse Temperature Dependence in Variation-Tolerant Nanoscale Systems with High-k Dielectrics and Metal Gates
    Wolpert, David
    Ampadu, Paul
    NANO-NET, 2009, 3 : 14 - 18
  • [23] Strained SiGe Channels for Band-Edge PMOS Threshold Voltages With Metal Gates and High-k Dielectrics
    Gilmer, David C.
    Schaeffer, Jamie K.
    Taylor, W. J.
    Capasso, C.
    Junker, Kurt
    Hildreth, Jill
    Tekleab, Daniel
    Winstead, Brian
    Samavedam, S. B.
    IEEE TRANSACTIONS ON ELECTRON DEVICES, 2010, 57 (04) : 898 - 904
  • [24] Influence of metal gate materials and processing on planar CMOS device characteristics with high-k gate dielectrics
    Majhi, P
    Young, C
    Bersuker, G
    Wen, HC
    Brown, GA
    Foran, B
    Choi, R
    Zeitzoff, PM
    Huff, HR
    ESSDERC 2004: PROCEEDINGS OF THE 34TH EUROPEAN SOLID-STATE DEVICE RESEARCH CONFERENCE, 2004, : 185 - 188
  • [25] Alternative High-k Dielectrics for Metal-Insulator-Metal Applications
    Lukosius, M.
    Kaynak, C. Baristiran
    Wenger, Ch
    Rushworth, S.
    PHYSICS AND TECHNOLOGY OF HIGH-K MATERIALS 8, 2010, 33 (03): : 15 - 23
  • [26] High-k/Metal Gates in Leading Edge Silicon Devices
    James, Dick
    2012 23RD ANNUAL SEMI ADVANCED SEMICONDUCTOR MANUFACTURING CONFERENCE (ASMC), 2012, : 346 - 353
  • [27] Molecular-beam deposition of high-k gate dielectrics for advanced CMOS
    Dimoulas, A
    MATERIALS FOR INFORMATION TECHNOLOGY: DEVICES, INTERCONNECTS AND PACKAGING, 2005, : 3 - 15
  • [28] High-K gate dielectrics for sub-100 nm CMOS technology
    Lee, SJ
    Lee, CH
    Kim, YH
    Luan, HF
    Bai, WP
    Jeon, TS
    Kwong, DL
    SOLID-STATE AND INTEGRATED-CIRCUIT TECHNOLOGY, VOLS 1 AND 2, PROCEEDINGS, 2001, : 303 - 308
  • [29] Nanoscale and device level reliability of high-k dielectrics based CMOS nanodevices
    Aguilera, L.
    2007 Spanish Conference on Electron Devices, Proceedings, 2007, : 162 - 164
  • [30] Low voltage SILC Analysis for High-k/Metal Gate Dielectrics
    Rahim, N.
    Misra, D.
    ADVANCED GATE STACK, SOURCE/DRAIN, AND CHANNEL ENGINEERING FOR SI-BASED CMOS 5: NEW MATERIALS, PROCESSES, AND EQUIPMENT, 2009, 19 (01): : 283 - 287