An adaptive viterbi decoder on the dynamically reconfigurable processor

被引：6
|
作者：
Abe, Sbobei
Hasegawa, Yohei
Toi, Takao
Inuo, Takeshi
Amano, Hidebaru
机构：
[1] Keio Univ, Dept Informat & Comp Sci, Yokohama, Kanagawa 223, Japan
[2] NEC Syst Devices Res Labs, Kawasaki, Kanagawa 2118668, Japan
来源：
2006 IEEE INTERNATIONAL CONFERENCE ON FIELD PROGRAMMABLE TECHNOLOGY, PROCEEDINGS | 2006年
关键词：
D O I：
10.1109/FPT.2006.270329
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
In order to evaluate practical adaptive computing on dynamically reconfigurable processors, several Viterbi decoders with different constraint variables are implemented on NEC Electronics' DRP-1. By switching designs, its throughput varies from 4.71 Mbps to 9.95 Mbps and its power consumption does from 423.93 mW to 1028.97 mW at the fixed throughput in response to the Signal to Noise Ratio. The power can be saved up to 58.3% and the throughput can be improved 2.1 times by switching designs appropriately when the distance of the base station and the mobile terminal is not very long.
引用
收藏
页码：285 / 288
页数：4
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