An adaptive viterbi decoder on the dynamically reconfigurable processor

被引：6
|
作者：
Abe, Sbobei
Hasegawa, Yohei
Toi, Takao
Inuo, Takeshi
Amano, Hidebaru
机构：
[1] Keio Univ, Dept Informat & Comp Sci, Yokohama, Kanagawa 223, Japan
[2] NEC Syst Devices Res Labs, Kawasaki, Kanagawa 2118668, Japan
来源：
2006 IEEE INTERNATIONAL CONFERENCE ON FIELD PROGRAMMABLE TECHNOLOGY, PROCEEDINGS | 2006年
关键词：
D O I：
10.1109/FPT.2006.270329
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
In order to evaluate practical adaptive computing on dynamically reconfigurable processors, several Viterbi decoders with different constraint variables are implemented on NEC Electronics' DRP-1. By switching designs, its throughput varies from 4.71 Mbps to 9.95 Mbps and its power consumption does from 423.93 mW to 1028.97 mW at the fixed throughput in response to the Signal to Noise Ratio. The power can be saved up to 58.3% and the throughput can be improved 2.1 times by switching designs appropriately when the distance of the base station and the mobile terminal is not very long.
引用
收藏
页码：285 / 288
页数：4
相关论文
共 50 条
  • [21] An energy-efficient reconfigurable viterbi decoder on a programmable multiprocessor
    Zhong, Guichang
    Willson, Alan N., Jr.
    2007 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS, VOLS 1-11, 2007, : 1565 - 1568
  • [22] An Adaptive Joint Viterbi Detector Decoder (AJVDD)
    Alappat, Vintu Jose
    Motani, Mehul
    Sann, Chan Kheong
    2016 10TH INTERNATIONAL CONFERENCE ON SIGNAL PROCESSING AND COMMUNICATION SYSTEMS (ICSPCS), 2016,
  • [23] RACER: A reconfigurable constraint-length 14 Viterbi Decoder
    Yeh, D
    Feygin, G
    Chow, P
    IEEE SYMPOSIUM ON FPGAS FOR CUSTOM COMPUTING MACHINES, PROCEEDINGS, 1996, : 60 - 69
  • [24] Reconfigurable Efficient Design of Viterbi Decoder for Wireless Communication Systems
    Gupta, Swati
    Mehra, Rajesh
    INTERNATIONAL JOURNAL OF ADVANCED COMPUTER SCIENCE AND APPLICATIONS, 2011, 2 (07) : 132 - 136
  • [25] Design and analysis of a dynamically reconfigurable network processor
    Troxel, IA
    George, AD
    Oral, S
    LCN 2002: 27TH ANNUAL IEEE CONFERENCE ON LOCAL COMPUTER NETWORKS, PROCEEDINGS, 2002, : 483 - 492
  • [26] A modeling of a dynamically reconfigurable processor using SystemC
    Kitamichi, Junji
    Ueda, Koji
    Kuroda, Kenichi
    21ST INTERNATIONAL CONFERENCE ON VLSI DESIGN: HELD JOINTLY WITH THE 7TH INTERNATIONAL CONFERENCE ON EMBEDDED SYSTEMS, PROCEEDINGS, 2008, : 91 - +
  • [27] A dynamically reconfigurable SIMD processor for a vision chip
    Komuro, T
    Kagami, S
    Ishikawa, M
    IEEE JOURNAL OF SOLID-STATE CIRCUITS, 2004, 39 (01) : 265 - 268
  • [28] Dynamically Reconfigurable Multi-Processor Arrays
    Glenn-Anderson, James
    CONFERENCE RECORD OF THE 2014 FORTY-EIGHTH ASILOMAR CONFERENCE ON SIGNALS, SYSTEMS & COMPUTERS, 2014, : 1858 - 1863
  • [29] Implementation of a UMTS turbo decoder on a dynamically reconfigurable platform
    La Rosa, A
    Lavagno, L
    Passerone, C
    IEEE TRANSACTIONS ON COMPUTER-AIDED DESIGN OF INTEGRATED CIRCUITS AND SYSTEMS, 2005, 24 (01) : 100 - 106
  • [30] Configurable adaptive Viterbi decoder for GPRS, EDGE and Wimax
    Batcha, Mohamed Farid Noor
    Sha'ameri, Ahmad Zuri
    ICT-MICC: 2007 IEEE INTERNATIONAL CONFERENCE ON TELECOMMUNICATIONS AND MALAYSIA INTERNATIONAL CONFERENCE ON COMMUNICATIONS, VOLS 1 AND 2, PROCEEDINGS, 2007, : 237 - 241
12345