Capacitive inter-chip data and power transfer for 3-D VLSI

被引：77
|
作者：
Culurciello, Eugenio [1 ]
Andreou, Andreas G.
机构：
[1] Yale Univ, Dept Elect Engn, New Haven, CT 06520 USA
[2] Johns Hopkins Univ, Dept Elect & Comp Engn, Baltimore, MD 21218 USA
来源：
IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS | 2006年 / 53卷 / 12期
基金：
美国国家科学基金会; 美国国家航空航天局;
关键词：
AC coupling; capacitive coupling; chip-to-chip communication; multichip module; proximity communication; silicon-on-insulator (SOI); silicon-on-sapphire (SOS); threedimensional (3-D) integration;
D O I：
10.1109/TCSII.2006.885073
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
We report on inter-chip bidirectional communication and power transfer between two stacked chips. The experimental prototype system components were fabricated in a 0.5-mu m silicon-on-sapphire CMOS technology. Bi-directional communication between the two chips is experimentally measured at 1 Hz - 15 MHz. The circuits on the floating top chip are powered with capacitively coupled energy using a charge pump. This is the first demonstration of simultaneous nongalvanic power and data transfer between chips in a stack. The potential use in 3-D VLSI is aimed at reducing costs and complexity that are associated with galvanic inter-chip vias in 3-D integration.
引用
收藏
页码：1348 / 1352
页数：5
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