Capacitive inter-chip data and power transfer for 3-D VLSI

被引：76

作者：

Culurciello, Eugenio ^{[1
]}

Andreou, Andreas G.

机构：

[1] Yale Univ, Dept Elect Engn, New Haven, CT 06520 USA

[2] Johns Hopkins Univ, Dept Elect & Comp Engn, Baltimore, MD 21218 USA

来源：

IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS II-EXPRESS BRIEFS | 2006年 / 53卷 / 12期

基金：

美国国家科学基金会; 美国国家航空航天局;

关键词：

AC coupling; capacitive coupling; chip-to-chip communication; multichip module; proximity communication; silicon-on-insulator (SOI); silicon-on-sapphire (SOS); threedimensional (3-D) integration;

D O I：

10.1109/TCSII.2006.885073

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

We report on inter-chip bidirectional communication and power transfer between two stacked chips. The experimental prototype system components were fabricated in a 0.5-mu m silicon-on-sapphire CMOS technology. Bi-directional communication between the two chips is experimentally measured at 1 Hz - 15 MHz. The circuits on the floating top chip are powered with capacitively coupled energy using a charge pump. This is the first demonstration of simultaneous nongalvanic power and data transfer between chips in a stack. The potential use in 3-D VLSI is aimed at reducing costs and complexity that are associated with galvanic inter-chip vias in 3-D integration.

引用

页码：1348 / 1352

页数：5

共 50 条

[1] Inter-Chip Wiring Technology for 3-D LSI
Kurita, Yoichiro
Motohashi, Norikazu
Matsui, Satoshi
Soejima, Koji
Amakawa, Shuhei
Masu, Kazuya
Kawano, Masaya
[J]. ELECTROCHEMISTRY, 2009, 77 (09) : 812 - 817
[2] Inter-chip data transfer without wires
不详
[J]. ELECTRONICS WORLD, 2000, 106 (1768): : 272 - 272
[3] A 65fJ/b Inter-Chip Inductive-Coupling Data Transceivers Using Charge-Recycling Technique for Low-Power Inter-Chip Communication in 3-D System Integration
Niitsu, Kiichi
Kawai, Shusuke
Miura, Noriyuki
Ishikuro, Hiroki
Kuroda, Tadahiro
[J]. IEEE TRANSACTIONS ON VERY LARGE SCALE INTEGRATION (VLSI) SYSTEMS, 2012, 20 (07) : 1285 - 1294
[4] Modeling capacitive links for broadband inter-chip communication
Viitala, Olli
Flak, Jacek
Lindfors, Saska
[J]. 2007 NORCHIP, 2007, : 142 - 145
[5] Power reduction in high-speed inter-chip data communications
Kuroda, T
[J]. 2005 6TH INTERNATIONAL CONFERENCE ON ASIC PROCEEDINGS, BOOKS 1 AND 2, 2005, : 3 - 7
[6] A 50% power reduction in inductive-coupling transceiver for 3D-stacked inter-chip data link
Zhang, Li
Li, Tie
Wang, Baocun
Zou, Xuecheng
[J]. 7TH IEEE INTERNATIONAL NANOELECTRONICS CONFERENCE (INEC) 2016, 2016,
[7] Characteristics of a Novel Compliant Bump for 3-D Stacking With High-Density Inter-Chip Connections
Watanabe, Naoya
Asano, Tanemasa
[J]. IEEE TRANSACTIONS ON COMPONENTS PACKAGING AND MANUFACTURING TECHNOLOGY, 2011, 1 (01): : 83 - 91
[8] A novel "SMAFTI" package for inter-chip wide-band data transfer
Kurita, Yoichiro
Soejima, Koji
Kikuchi, Katsumi
Takahashi, Masatake
Tago, Masamoto
Koike, Masahiro
[J]. 56TH ELECTRONIC COMPONENTS & TECHNOLOGY CONFERENCE 2006, VOL 1 AND 2, PROCEEDINGS, 2006, : 289 - +
[9] Inductive Coupling Transceivers for Inter-chip Data Communication
Kuroda, Tadahiro
[J]. 2009 IEEE INTERNATIONAL SYMPOSIUM ON RADIO-FREQUENCY INTEGRATION TECHNOLOGY: SYNERGY OF RF AND IC TECHNOLOGIES, PROCEEDINGS, 2009, : 13 - 15
[10] Inter-Chip Data Transfer Capability of TSV-Free Interposer (TFI) Package
Kawano, Masaya
Lim, Teck-Guan
Li, Hong-Yu
[J]. 2018 IEEE 20TH ELECTRONICS PACKAGING TECHNOLOGY CONFERENCE (EPTC), 2018, : 151 - 157

← 1 2 3 4 5 →