Power reduction in high-speed inter-chip data communications

被引：0
|
作者：
Kuroda, T [1 ]
机构：
[1] Keio Univ, Dept Elect & Elect Engn, Yokohama, Kanagawa 223, Japan
来源：
2005 6TH INTERNATIONAL CONFERENCE ON ASIC PROCEEDINGS, BOOKS 1 AND 2 | 2005年
关键词：
D O I：
暂无
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
This paper describes power reduction techniques in high-speed inter-chip data communication with inductive coupled wireless interface for 3D-stacked SiP. NRZ signaling where signal is not transmitted when data holds reduces power dissipation in proportion to switching activity. A, low-power single-end transmitter is presented for 55% transmitter's power reduction. Depending on communication distance, transmit power is controlled for both power and crosstalk reduction. 195Gb/s, 1.2W high-speed and low-power interface with these techniques has been demonstrated in 0.25 mu m CMOS.
引用
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页码：3 / 7
页数：5
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