PLD MODELING OF ALL-DIGITAL DLL

被引：0

作者：

Svedek, Tomislav ^{[1
]}

Matic, Tomislav ^{[1
]}

Herceg, Marijan ^{[1
]}

机构：

[1] JJ Strossmayer Univ Osijek, Dept Commun, Fac Elect Engn, Osijek, Croatia

来源：

JOURNAL OF ELECTRICAL ENGINEERING-ELEKTROTECHNICKY CASOPIS | 2009年 / 60卷 / 05期

关键词：

all-digital DLL; PLD implementation; digital-controlled delay line;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

An all-digital delay-locked loop (DLL) suitable for implementation in the programmable logic device (PLD) is presented in this paper. Analog parts of the conventional DLL are realized by digital circuitry. Digital-controlled delay line (DCDL) is made of programmable digital-controlled delay elements (DCDE) based on the binary-weighted multiplex LCELL structures. Problems encountered in PLD implementation of the DLL are emphasized and discussed. Simulation and measuring results of the proposed DLL realized by ALTERA device EPM7128SLI10, are presented.

引用

页码：246 / 254

页数：9

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