共 45 条
- [41] Low Temperature (250°C) and Fine Pitch (≤4 μ m) New Nanocrystalline Cu/SiO2 Chip-on-Wafer Hybrid Bonding for 3D Chip Integration 2024 INTERNATIONAL VLSI SYMPOSIUM ON TECHNOLOGY, SYSTEMS AND APPLICATIONS, VLSI TSA, 2024,
- [43] Advanced 3D Packaging of Chips and Materials Integrity: Stress-Induced Effects and Mechanical Properties of New Ultra Low-k Dielectrics for On-Chip Interconnect Stacks MATERIALS STRUCTURE & MICROMECHANICS OF FRACTURE VII, 2014, 592-593 : 563 - 568