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An Ultra-Low Power Dual-Ring Factorial Delay Locked Loop in 28nm FD-SOI technology

被引：0
|
作者：
Hoang, Khoa [1 ]
Deval, Yann [1 ]
Rivet, Francois [1 ]
机构：
[1] Univ Bordeaux, IMS Lab, Bordeaux, France
来源：
2016 13TH IEEE INTERNATIONAL CONFERENCE ON SOLID-STATE AND INTEGRATED CIRCUIT TECHNOLOGY (ICSICT) | 2016年
关键词：
D O I：
暂无
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
This paper introduces a technique for balancing input and output timing of factorial ring owing to achieving higher accuracy as weil as reduction of counter delay and reference spurs. Besides, this design offers an 8-bit programmable counter for a more flexible frequency synthesizer. The initial objective was for generating a 2.5GHz signal. However, thanks to the wide tuning range of the Voltage Controlled Delay Elements (VCDEs), the system has output performance spreads from 1 to 3.5GHz. On full system simulation, the power consumption is approximately 150uW with power supply of 1 V. The system was implemented on 28nm FD-SOI with verifications by full-system simulations at transistor level.
引用
收藏
页码：557 / 559
页数：3
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