Energy-Delay Tradeoffs of Low-Voltage Dual Mode Logic in 28nm FD-SOI

被引：0

作者：

Taco, Ramiro ^{[1
]}

Levi, Itamar ^{[1
]}

Lanuzza, Marco ^{[2
]}

Fish, Alexander ^{[1
]}

机构：

[1] Bar Ilan Univ, Ramat Gan, Israel

[2] Univ Calabria, Arcavacata Di Rende, CS, Italy

来源：

2017 IEEE SOI-3D-SUBTHRESHOLD MICROELECTRONICS TECHNOLOGY UNIFIED CONFERENCE (S3S) | 2017年

基金：

以色列科学基金会;

关键词：

Dual mode logic (DML); low-voltage; carry skip adder; DESIGNS;

D O I：

暂无

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

In this paper, the Dual Mode Logic (DML) technique is evaluated on a low-voltage 16-bit Carry Skip Adder in 28 nm UTBB FD-SOI technology. By combining the operating characteristics of the DML and the unique features of the technology, energy/speed efficient low-voltage adder designs can be defined. More precisely, it is demonstrated that, the capability of the DML design to switch on-the-fly between static and dynamic modes of operation leads to an improvement of more than 20% in terms of energy-delay product (EDP) in comparison to the conventional CMOS design. Moreover, the high efficiency of back plane biasing in the adopted technology allows very fine tuning of energy-delay performances of a DML design, thus emphasizing its intrinsic versatility.

引用

页数：3

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