A flash EEPROM cell with self-aligned trench transistor & isolation structure

被引：2

作者：

Nakagawa, K ^{[1
]}

Yoshida, K ^{[1
]}

Masuda, S ^{[1
]}

Yoshino, A ^{[1
]}

Sakai, I ^{[1
]}

机构：

[1] NEC Corp Ltd, Ulsi Device Dev Lab, Sagamihara, Kanagawa 2291198, Japan

来源：

2000 SYMPOSIUM ON VLSI TECHNOLOGY, DIGEST OF TECHNICAL PAPERS | 2000年

关键词：

D O I：

10.1109/VLSIT.2000.852795

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

For future high-density contactless-NOR-type flash EEPROMs, a new memory cell with self-aligned trench transistor & isolation structure has been proposed, and its feasibility was demonstrated. The short channel effect was suppressed markedly down to the feature size (F) of 0.14 mu m with the tunnel oxide thickness of 9 nm and excellent endurance performance (>10(5) Fowler-Nordheim write/erase cycles) of the memory cell with the area of 0.16 mu m(2) (8F(2), F=0.14 mu m) was realized.

引用

页码：124 / 125

页数：2

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