A Latency Simulator for Many-core Systems

被引：0

作者：

Kumar, Sunil ^{[1
]}

Cucinotta, Tommaso ^{[2
]}

Lipari, Giuseppe ^{[2
]}

机构：

[1] LNM Inst Informat Technol, Jaipur, Rajasthan, India

[2] Scuola Super Sant Anna, Pisa, Italy

来源：

44TH ANNUAL SIMULATION SYMPOSIUM 2011 (ANSS 2011) - 2011 SPRING SIMULATION MULTICONFERENCE - BK 2 OF 8 | 2011年

关键词：

Simulation; Many-Core Architecture; Interconnect; Network-on-a-Chip; Latency; MODEL; NETWORKS; CHIP;

D O I：

暂无

中图分类号：

TP301 [理论、方法];

学科分类号：

081202 ;

摘要：

In this paper we present MCoreSim, an open-source simulation framework for massively parallel and many-core computing systems based on OMNeT++. The simulator supports tile-based architectures with distributed memory and mesh based interconnects. Its primary purpose is to allow for investigations on the impact of the heterogeneous in-chip communication latencies, as arising due to the network-on-a-chip structure of future and emerging many-core processors, on the performance of the hosted applications. We plan to use MCoreSim to study the variety of possible choices in realizing a suitable software stack for these systems, especially in terms of the choices at the kernel design level.

引用

页码：151 / 158

页数：8

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