Realization of multi-level partial response modem in reconfigurable logic

被引：0

作者：

Pienaar, JF ^{[1
]}

Linde, LP ^{[1
]}

Marx, FE ^{[1
]}

机构：

[1] Univ Pretoria, Dept Elect Elect & Comp Engn, Pretoria, South Africa

来源：

2002 IEEE AFRICON, VOLS 1 AND 2: ELECTROTECHNOLOGICAL SERVICES FOR AFRICA | 2002年

关键词：

D O I：

10.1109/AFRCON.2002.1146827

中图分类号：

TP [自动化技术、计算机技术];

学科分类号：

0812 ;

摘要：

Hardware realization is an important issue in communications system design. The use of high density reconfigurable logic instead of traditional DSP based solutions is investigated. The case of a multi-level partial response modem is discussed in this paper. The practical logic structures of the internal modem components including equalizer, Viterbi decoder and FIR filters are presented. Results of the hardware implementation are also presented.

引用

页码：167 / 172

页数：6

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