A CMOS Analog Front-End for Driving a High-Speed SAR ADC in Low-Power Ultrasound Imaging

In recent studies of ultrasound imaging systems, successive approximation register ( SAR) analog-to-digital converters (ADCs) are suggested as an alternative architecture for low-power ultrasound receiver integrated circuits. However, the sampling period of a high-speed SAR ADC is very short -less than a few nanoseconds. This results in the need of a very wide unity-gain bandwidth of the amplifier in the anti-aliasing filter (AAF), and it also causes more serious kick-back noise. In this paper, a single-channel analog front-end (AFE) with a RC filter for a high-speed SAR ADC is presented. The RC filter relaxes the bandwidth requirement of the amplifier in the AAF by 16% and reduces kick-back noise coming from the ADC input. The proposed AFE is fabricated in 0.18 mu m CMOS process. The design achieves 5.05nV/root Hz input-referred noise density and the voltage gain is controlled in the range of [-3.02, 30.6] dB in a linear- in- dB scale with 16 steps by a 4-bit digital code. Our AFE circuit consumes 30mA from a 1.8V supply.