VHDL-based simulation environment for proteo NoC

被引：5

作者：

Sigüenza-Tortosa, D ^{[1
]}

Nurmi, J ^{[1
]}

机构：

[1] Tampere Univ Technol, IDCS, FIN-33101 Tampere, Finland

来源：

SEVENTH IEEE INTERNATIONAL HIGH-LEVEL DESIGN VALIDATION AND TEST WORKSHOP, PROCEEDINGS | 2002年

关键词：

D O I：

10.1109/HLDVT.2002.1224419

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

The purpose of this paper is to present the work that has been carried out for the creation of a simulation environment of our Network-on-Chip (NoC) architecture, called "Proteo". In an Intellectual Property (1P) based design methodology also the interconnection structures may be treated as IPs. The Proteo project is aimed at creating a library of pre-designed communication blocks that can be selected from a component library and configured by automated tools. The network implements packet switching in a hierarchical topology. We have created a high level model of our network in VHM allowing mixed-abstraction level simulation of our synthesizable code for validation.

引用

页码：1 / 6

页数：6

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