An Analog-Node Model for VHDL-Based Simulation of RF Integrated Circuits

被引:6
|
作者
Schubert, Martin J. W. [1 ]
机构
[1] Regensburg Univ Appl Sci, D-93053 Regensburg, Germany
关键词
Analog; mixed signal; modeling; RF; RF integrated circuit (RFIC); simulation; system on a chip (SoC); verification; very-high-speed integrated-circuit hardware description language (VHDL); PHASE NOISE; JITTER; CLOCK; AMS;
D O I
10.1109/TCSI.2009.2027799
中图分类号
TM [电工技术]; TN [电子技术、通信技术];
学科分类号
0808 ; 0809 ;
摘要
This paper describes a very-high-speed integrated-circuit hardware description language (VHDL)-based analog-node model, an associated driver component for the mixed-signal event-driven (MixED) simulation technique, and some primitive device models applied to radio-frequency integrated circuits. With the presented MixED method, analog circuits are modeled as a composition of controlled sources. Unlike other VHDL-based analog simulation methods, these MixED sources compute not only a real number representing an output voltage but also an output impedance. This allows the outputs of several MiXED sources to be connected in order to drive the same node signal. The voltage of this record-type signal is automatically computed at its element by resolution functions in compliance with Kirchhoff's current law. The data structure of the node signal, its self-defined resolution functions, and an associated driver component are presented and discussed to meet different simulation requirements, such as speed, versatility, current accuracy, and adaptive time stepping. Several examples demonstrate how to behaviorally model mixed-signal components with this method with an emphasis on the simulation of a heterodyne receiver. Simulation speeds are compared to VHDL-AMS tools.
引用
收藏
页码:2717 / 2727
页数:11
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