VHDL-based simulation environment for proteo NoC

被引：5
|
作者：
Sigüenza-Tortosa, D [1 ]
Nurmi, J [1 ]
机构：
[1] Tampere Univ Technol, IDCS, FIN-33101 Tampere, Finland
来源：
SEVENTH IEEE INTERNATIONAL HIGH-LEVEL DESIGN VALIDATION AND TEST WORKSHOP, PROCEEDINGS | 2002年
关键词：
D O I：
10.1109/HLDVT.2002.1224419
中图分类号：
TP3 [计算技术、计算机技术];
学科分类号：
0812 ;
摘要：
The purpose of this paper is to present the work that has been carried out for the creation of a simulation environment of our Network-on-Chip (NoC) architecture, called "Proteo". In an Intellectual Property (1P) based design methodology also the interconnection structures may be treated as IPs. The Proteo project is aimed at creating a library of pre-designed communication blocks that can be selected from a component library and configured by automated tools. The network implements packet switching in a hierarchical topology. We have created a high level model of our network in VHM allowing mixed-abstraction level simulation of our synthesizable code for validation.
引用
收藏
页码：1 / 6
页数：6
相关论文
共 50 条
  • [21] VHDL-Based FPGA/CPLD Design Optimization Research
    Pang, Xuemin
    Yu, Daojie
    Guo, Yuhua
    Zhou, Changlin
    [J]. MECHATRONICS AND INTELLIGENT MATERIALS II, PTS 1-6, 2012, 490-495 : 860 - 864
  • [22] Intrinsic and extrinsic attributes for VHDL-based CAD environments
    Venkatesan, S
    Davis, KC
    [J]. PROCEEDINGS OF THE 9TH INTERNATIONAL CONFERENCE ON COMPUTER APPLICATIONS IN INDUSTRY AND ENGINEERING, 1996, : 107 - 110
  • [23] A VHDL-based approach for power estimation of embedded systems
    Fornaciari, W
    Gubian, P
    Sciuto, D
    Silvano, C
    [J]. JOURNAL OF SYSTEMS ARCHITECTURE, 1997, 44 (01) : 37 - 61
  • [24] VHDL-based expert system for hardware synthesis - an overview
    Shiva, Sajjan G.
    Jones, Judit U.
    [J]. Computing and Control Engineering Journal, 1993, 4 (02): : 85 - 91
  • [25] VHDL-BASED SIMULATOR BOOSTS DESIGN PRODUCTIVITY TENFOLD
    LEONARD, M
    [J]. ELECTRONIC DESIGN, 1988, 36 (11) : 63 - 64
  • [26] VHDL-based EDA tool implementation with Java']Java
    Miller, R
    [J]. PROCEEDINGS OF THE 8TH GREAT LAKES SYMPOSIUM ON VLSI, 1998, : 440 - 445
  • [27] VHDL-based Modelling Approach for the Digital Simulation of 4-phase Adiabatic Logic Design
    Maheshwari, Sachin
    Bartlett, Viv A.
    Kale, Izzet
    [J]. 2018 28TH INTERNATIONAL SYMPOSIUM ON POWER AND TIMING MODELING, OPTIMIZATION AND SIMULATION (PATMOS), 2018, : 111 - 117
  • [28] Towards a VHDL-based synthesis of a wavelet transform processor
    Ferretti, M
    Rizzo, D
    [J]. CAMP'97 - FOURTH IEEE INTERNATIONAL WORKSHOP ON COMPUTER ARCHITECTURE FOR MACHINE PERCEPTION, PROCEEDINGS, 1997, : 295 - 299
  • [29] VHDL-based FPGA Implementation of C/E System
    Lu, Jiyuan
    Jing, Liang
    [J]. INTERNATIONAL WORKSHOP ON AUTOMOBILE, POWER AND ENERGY ENGINEERING, 2011, 16
  • [30] Modelling, simulation and verification of 4-phase adiabatic logic design: A VHDL-Based approach
    Maheshwari, Sachin
    Bartlett, V. A.
    Kale, Izzet
    [J]. INTEGRATION-THE VLSI JOURNAL, 2019, 67 : 144 - 154
12345