Bipolar Transistor Excess Phase Modeling in Verilog-A

被引：4

作者：

McAndrew, Colin C. ^{[1
]}

Huszka, Zoltan ^{[2
]}

Coram, Geoffrey J. ^{[3
]}

机构：

[1] Freescale Semicond, Tempe, AZ 85284 USA

[2] Austriamicrosyst AG, A-8141 Unterpremstatten, Unterpremstaett, Austria

[3] Analog Devices Inc, Wilmington, MA USA

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 2009年 / 44卷 / 09期

关键词：

Bipolar transistors; circuit simulation; semiconductor device modeling; SPICE;

D O I：

10.1109/JSSC.2009.2022667

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

The collector current I-c of a bipolar transistor does not instantaneously respond to changes in applied base-emitter voltage V-be; its response exhibits a time lag because of the finite transit time of carriers through the transistor, which is manifest as a phase lag (or "excess phase") in the frequency domain. In this paper we present an excess phase model that has a constant magnitude response, in contrast to previous models which introduce a change in magnitude as well as in phase, and detail how our model can be implemented in Verilog-A. In addition, we show how a bias dependence of the time lag can be added to the Verilog-A implementation of the Weil-McNamee excess phase model without introducing undesired behavior.

引用

下载

页码：2267 / 2275

页数：9

共 50 条

[1] Verilog-A Modeling of BJT NQS Excess Phase
McAndrew, Colin C.
Huszka, Zoltan
Coram, Geoffrey
PROCEEDINGS OF THE 2008 BIPOLAR/BICMOS CIRCUITS AND TECHNOLOGY MEETING, 2008, : 73 - +
[2] Phase change memory modeling using Verilog-A
Liao, Yi-Bo
Chen, Yan-Kai
Chiang, Meng-Hsueh
BMAS 2007: PROCEEDINGS OF THE 2007 IEEE INTERNATIONAL BEHAVIORAL MODELING AND SIMULATION WORKSHOP, 2007, : 159 - +
[3] Modeling and simulation of a MOSFET transistor in Verilog-A considering parasite elements.
Ghandy Vladimir, Cruz Dominguez
Juarez Manuel, Tlapa
Barranco Hector, Bonilla
Torillo Erwin, Zuniga
Morales Felix, Quirino
Maria Fernanda, Lopez Arauz
2015 IEEE Workshop on Power Electronics and Power Quality Applications (PEPQA), 2015,
[4] Behavioral Verilog-A Model of Superconductor-Ferromagnetic Transistor
Krylov, Gleb
Friedman, Eby G.
2018 IEEE INTERNATIONAL SYMPOSIUM ON CIRCUITS AND SYSTEMS (ISCAS), 2018,
[5] Modeling of Silicon Photonics Devices with Verilog-A
Martin, P.
Gays, F.
Grellier, E.
Myko, A.
Menezo, S.
2014 29TH INTERNATIONAL CONFERENCE ON MICROELECTRONICS PROCEEDINGS - MIEL 2014, 2014, : 209 - 212
[6] Best Practices for Compact Modeling in Verilog-A
McAndrew, Colin C.
Coram, Geoffrey J.
Gullapalli, Kiran K.
Jones, J. Robert
Nagel, Laurence W.
Roy, Ananda S.
Roychowdhury, Jaijeet
Scholten, Andries J.
Smit, Geert D. J.
Wang, Xufeng
Yoshitomi, Sadayuki
IEEE JOURNAL OF THE ELECTRON DEVICES SOCIETY, 2015, 3 (05): : 383 - 396
[7] Verilog-A Modeling of Organic Electrochemical Transistors
Sideris, P.
Siskos, S.
Malliaras, G.
2017 6TH INTERNATIONAL CONFERENCE ON MODERN CIRCUITS AND SYSTEMS TECHNOLOGIES (MOCAST), 2017,
[8] Verilog-A modeling of SPAD for circuit simulations
Yang Hong-jiao
Jin Xiang-liang
Zhou Xiao-ya
Chen Chang-ping
Luo Jun
INTERNATIONAL SYMPOSIUM ON PHOTOELECTRONIC DETECTION AND IMAGING 2013: IMAGING SENSORS AND APPLICATIONS, 2013, 8908
[9] Modeling of Graphene Nanoribbon Tunnel Field Effect Transistor in Verilog-A for Digital Circuit Design
Fahad, Md
Zhao, Zhou
Srivastava, Ashok
Peng, Lu
PROCEEDINGS OF 2016 IEEE INTERNATIONAL SYMPOSIUM ON NANOELECTRONIC AND INFORMATION SYSTEMS (INIS), 2016, : 1 - 5
[10] Modeling a wireless IF sampling circuit in Verilog-A
Kundert, K
Filseth, E
COMPUTER DESIGN, 1996, 35 (01): : 102 - 104

← 1 2 3 4 5 →