Bipolar Transistor Excess Phase Modeling in Verilog-A

The collector current I-c of a bipolar transistor does not instantaneously respond to changes in applied base-emitter voltage V-be; its response exhibits a time lag because of the finite transit time of carriers through the transistor, which is manifest as a phase lag (or "excess phase") in the frequency domain. In this paper we present an excess phase model that has a constant magnitude response, in contrast to previous models which introduce a change in magnitude as well as in phase, and detail how our model can be implemented in Verilog-A. In addition, we show how a bias dependence of the time lag can be added to the Verilog-A implementation of the Weil-McNamee excess phase model without introducing undesired behavior.