Bipolar Transistor Excess Phase Modeling in Verilog-A

被引：4

作者：

McAndrew, Colin C. ^{[1
]}

Huszka, Zoltan ^{[2
]}

Coram, Geoffrey J. ^{[3
]}

机构：

[1] Freescale Semicond, Tempe, AZ 85284 USA

[2] Austriamicrosyst AG, A-8141 Unterpremstatten, Unterpremstaett, Austria

[3] Analog Devices Inc, Wilmington, MA USA

来源：

IEEE JOURNAL OF SOLID-STATE CIRCUITS | 2009年 / 44卷 / 09期

关键词：

Bipolar transistors; circuit simulation; semiconductor device modeling; SPICE;

D O I：

10.1109/JSSC.2009.2022667

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

The collector current I-c of a bipolar transistor does not instantaneously respond to changes in applied base-emitter voltage V-be; its response exhibits a time lag because of the finite transit time of carriers through the transistor, which is manifest as a phase lag (or "excess phase") in the frequency domain. In this paper we present an excess phase model that has a constant magnitude response, in contrast to previous models which introduce a change in magnitude as well as in phase, and detail how our model can be implemented in Verilog-A. In addition, we show how a bias dependence of the time lag can be added to the Verilog-A implementation of the Weil-McNamee excess phase model without introducing undesired behavior.

引用

页码：2267 / 2275

页数：9

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