Thermal stress analysis of the low-k layer in a flip-chip package

被引：9

作者：

Wang, L. ^{[1
,2
,3
]}

Xu, C. ^{[2
]}

Lin, L. ^{[1
]}

Yang, C. ^{[1
]}

Wang, J. ^{[1
]}

Xiao, F. ^{[1
]}

Zhang, W. ^{[2
,3
]}

机构：

[1] Fudan Univ, Dept Mat Sci, Shanghai 200433, Peoples R China

[2] Natl Ctr Adv Packaging, Bldg D1,200 Linghu Blvd, Wuxi 214135, Jiangsu, Peoples R China

[3] Chinese Acad Sci, Inst Microelect, Beijing 100029, Peoples R China

来源：

MICROELECTRONIC ENGINEERING | 2016年 / 163卷

关键词：

Finite elements analysis; Reliability; Low-k layer; Chip package interaction; Dielectric crack;

D O I：

10.1016/j.mee.2016.06.007

中图分类号：

TM [电工技术]; TN [电子技术、通信技术];

学科分类号：

0808 ; 0809 ;

摘要：

The structural integrity on low-k layers is a major reliability concern on three-dimensional packaging technology. The low-k material used in dies has a reduced stiffness and adhesion strength to the barrier materials, which makes the back-end-of-line (BEOL) structure much more vulnerable to the externally applied thermal stress during the flip-chip packaging. This thermal stress can cause a serious impact on the reliability and yield of electronic components, and hence the stress optimization is required. This paper aims to create an equivalent thermal stress model to evaluate the stress conditions in different low-k layers generated during the assembly. The model has only one sub-model and is verified by the flip-chip assembly of a 40 nm technology node chip. It is shown that this thermal stress model has the potential to predict the stress variation tendency in the different BEOL layers and hence can be used for the chip packaging interaction study. (C) 2016 Elsevier B.V. All rights reserved.

引用

页码：78 / 82

页数：5

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