Digital decimation filter design and simulation for delta-sigma ADC with high performance

被引：1
|
作者：
Li Hongqin [1 ]
机构：
[1] Shanghai Univ Engn Sci, Shanghai 201620, Peoples R China
来源：
ASICON 2007: 2007 7TH INTERNATIONAL CONFERENCE ON ASIC, VOLS 1 AND 2, PROCEEDINGS | 2007年
关键词：
digital decimation filter; delta-sigma ADC; FIR filter;
D O I：
10.1109/ICASIC.2007.4415782
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
This paper study a kind of design method about the digital decimation filter design for delta-Sigma ADC with high performance and validated it by simulation using MATLAB tool. A 16-bit digital decimation filter design for stereo audio delta-sigma ADC has been developed. A two-stage decimation filter architecture which can reduce digital switching noise was,also introduced in this design. A merged four-stage comb filter is used for the first stage, and a bit-serial finite-impulse-response (FIR) filter is used for the second stage. In addition, a high pass filter is used to compensate filter's DC offset. The design simulated using MATLAB according to this scheme can achieve higher performances.
引用
收藏
页码：922 / 925
页数：4
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