High-speed decimation filter for delta-sigma analog to-digital converter

被引：1
|
作者：
Xie, YP [1 ]
Whiteley, SR
Van Duzer, T
机构：
[1] Univ Calif Berkeley, Dept Elect Engn & Comp Sci, Berkeley, CA 94720 USA
[2] Univ Calif Berkeley, Elect Res Lab, Berkeley, CA 94720 USA
来源：
IEEE TRANSACTIONS ON APPLIED SUPERCONDUCTIVITY | 1999年 / 9卷 / 02期
关键词：
D O I：
10.1109/77.783815
中图分类号：
TM [电工技术]; TN [电子技术、通信技术];
学科分类号：
0808 ; 0809 ;
摘要：
A 12-bit digital filter is designed for an A/D converter system with sampling speed of 16 GHz. Data stream of 16 Gbit/s from delta-sigma modulator will pass through a 1:4 demultiplexer. Pour identical 12-bit digital filters are used to catch the data streams from the demultiplexer for 4 Gbit/s in each channel. The 12-bit superconductive digital filter is designed with modified variable threshold logic (MVTL) gates. A novel SOR gate is designed and used in this circuit to reduce circuit complexity. and improve performance. Progress of high speed testing results is presented. The filter comprises 583 Josephson junctions and consumes about 1 mW power.
引用
收藏
页码：3632 / 3635
页数：4
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