Decimation filter of the delta-sigma analog-to-digital converter with ternary data encoding

被引：0
|
作者：
Morozov D.V. [1 ]
Pilipko M.M. [1 ]
Korotkov A.S. [1 ]
机构：
[1] St. Petersburg State Polytechnical University
来源：
Russian Microelectronics | 2011年 / 40卷 / 5期
关键词：
Clock Frequency; RUSSIAN Microelectronics; Transmission Band; Amplitude Frequency Characteristic; Infinite Impulse Response Filter;
D O I：
10.1134/S1063739711050064
中图分类号：
学科分类号：
摘要：
The results of the development of a decimation filter of an analog-to-digital converter with ternary data encoding are presented. The filter reduces the clock frequency of the delta-sigma modulator of 100 MHz by a factor of 27. The proposed circuit engineering solutions are designed for manufacturing using the standard 0.18 μm MOS technology and the bipolar supply of ±0.9 V. The performance capability of the circuits is confirmed by the results of functional and circuit simulation using MatLab and Cadence Design Systems software. © 2011 Pleiades Publishing, Ltd.
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收藏
页码：352 / 360
页数：8
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