Digital decimation filter design for Sigma-Delta ADC

ADC as a link between analog and digital circuits, it plays an important role in the on-chip system. In addition to the static and dynamic index, area and power consumption have become a primary concern in the design parameters. Sigma-Delta ADC was composed of a Sigma-Delta modulator and a digital decimation filter, area and power consumption are mainly determined by digital sampling filter. In this paper, digital decimation filter was composed of a CIC filter, a FIR compensation filter and a Half-Band decimation filter. CIC filter working under a high sampling frequency will consume large amounts of power. The FIR compensation filter and the Half-Band decimation filter require a lot of memory to store filter coefficients which will increase the consumption of the area. In order to solve the above problems, we must improve the structure of the filter. The main purpose of this paper is using MATLAB to design a low power consumption and small area digital decimation filter to apply to the Sigma-Delta ADC. This paper in 0.18 um CMOS process, designs a digital decimation filter, the input sampling frequency is 1024 kHz and the output sampling frequency is 2 kHz and the output bit width is 18 bit.