Design of a digital decimation filter for high-precision 4-order Sigma-Delta ADC

被引：1
|
作者：
Chen Weiping [1 ]
Qiang, Fu [1 ]
Liu Xiaowei [1 ]
Yan, Xiao [1 ]
Bin, Zhang [1 ]
Yang Yuheng [1 ]
机构：
[1] Harbin Inst Technol, MEMS Ctr, Harbin 150006, Heilongjiang, Peoples R China
来源：
MICRO-NANO TECHNOLOGY XIII | 2012年 / 503卷
关键词：
Sigma-Delta ADC; digital decimation filter; CSD;
D O I：
10.4028/www.scientific.net/KEM.503.415
中图分类号：
TB3 [工程材料学];
学科分类号：
0805 ; 080502 ;
摘要：
In this paper, a design of a digital decimation filter which has a output of 24 bits for high-precision 4-ordes Sigma-Delta ADC is proposed. The digital decimation filter includes a CIC filter, a compensation filter and a half band filter. The over-sampling rate of the digital decimation filter is 256, the cutoff frequency is 1kHz, the coefficient of the pass-band ripple is -0.25dB, the stop-band attenuation is -162dB, simulation results using Mat lab and modelsim are correct, the result of the FPGA verification shows that the design meet the requirement of the high-precision 4-ordes Sigma-Delta ADC.
引用
收藏
页码：415 / 419
页数：5
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