Low-power area-efficient pipelined A/D converter design using a single-ended amplifier

This paper presents a new scheme of a low-power area-efficient pipelined A/D converter using a single-ended amplifier. The proposed multiply-by-two single-ended amplifier using switched capacitor circuits has smaller DC bias current compared to the conventional fully-differential scheme, and has a small capacitor mismatch sensitivity, allowing us to use a smaller capacitance. The simple high-gain dynamic-biased regulated cascode amplifier also has an excellent switching response. These properties lead to the low-power area-efficient design of highspeed A/D converters. The estimated power dissipation of the 10b pipelined A/D converter is less than 12 mW at 20 MSample/s.