Minimal march tests for unlinked static faults in Random Access Memories

被引：30

作者：

Harutunyan, G ^{[1
]}

Vardanian, VA ^{[1
]}

Zorian, Y ^{[1
]}

机构：

[1] Virage Log, Yerevan 375010, Armenia

来源：

23RD IEEE VLSI TEST SYMPOSIUM, PROCEEDINGS | 2005年

关键词：

D O I：

10.1109/VTS.2005.56

中图分类号：

TP3 [计算技术、计算机技术];

学科分类号：

0812 ;

摘要：

New minimal March test algorithms are proposed for detection of (all) unlinked static faults in Random Access Memories. In particular, a new minimal March MSS test of complexity 18N is introduced detecting all realistic simple static faults, as March SS (22N), (S. Hamdioui, van de Goor, Rodgers, MTDT 2002).

引用

页码：53 / 59

页数：7

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[41] RANDOM TESTING OF STATIC MEMORIES
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[42] OPTIMAL ALGORITHM FOR TESTING STUCK-AT FAULTS IN RANDOM-ACCESS MEMORIES - COMMENT
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[J]. JOURNAL OF ELECTRONIC TESTING-THEORY AND APPLICATIONS, 1994, 5 (04): : 347 - 365
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