共 50 条
- [21] Suppressing Dead-Time Effect in Current- Controlled Three-Phase PWM Inverters by Using Virtual Inductor [J]. THIRTY-THIRD ANNUAL IEEE APPLIED POWER ELECTRONICS CONFERENCE AND EXPOSITION (APEC 2018), 2018, : 867 - 871
- [26] A Development of 6kV Three-Level NPC Inverters with Novel DC-Link Circuit and Optimal Dead-Time Configuration [J]. 2012 IEEE INTERNATIONAL SYMPOSIUM ON INDUSTRIAL ELECTRONICS (ISIE), 2012, : 1957 - 1961
- [27] Impact and Compensation of Dead Time on Common Mode Voltage Elimination Modulation for Neutral-Point-Clamped Three-Phase Inverters [J]. 2013 IEEE ECCE ASIA DOWNUNDER (ECCE ASIA), 2013, : 1016 - 1022